^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * OMAP3 Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP34XX_CM_IDLEST_VAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * in the same register at a bit offset of 0x8. The EN_ACK for ICK is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * at an offset of 4 from ICK enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AM35XX_IPSS_ICK_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AM35XX_IPSS_ICK_EN_ACK_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AM35XX_IPSS_ICK_FCK_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AM35XX_IPSS_CLK_IDLEST_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AM35XX_ST_IPSS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @clk: struct clk * being enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * from the CM_{I,F}CLKEN bit. Pass back the correct info via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @idlest_reg and @idlest_bit. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 *idlest_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 *idlest_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) idlest_reg->offset &= ~0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) idlest_reg->offset |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *idlest_val = OMAP34XX_CM_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .allow_idle = omap2_clkt_iclk_allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .deny_idle = omap2_clkt_iclk_deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .find_idlest = omap3430es2_clk_ssi_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .find_companion = omap2_clk_dflt_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @clk: struct clk * being enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * target IDLEST bits. For our purposes, we are concerned with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * target IDLEST bits, which exist at a different bit position than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * the *CLKEN bit position for these modules (DSS and USBHOST) (The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * default find_idlest code assumes that they are at the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * position.) No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 *idlest_bit, u8 *idlest_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) idlest_reg->offset &= ~0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) idlest_reg->offset |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* USBHOST_IDLE has same shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *idlest_val = OMAP34XX_CM_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .find_companion = omap2_clk_dflt_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .allow_idle = omap2_clkt_iclk_allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .deny_idle = omap2_clkt_iclk_deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .find_companion = omap2_clk_dflt_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @clk: struct clk * being enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @idlest_reg and @idlest_bit. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 *idlest_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 *idlest_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) idlest_reg->offset &= ~0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) idlest_reg->offset |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *idlest_val = OMAP34XX_CM_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .allow_idle = omap2_clkt_iclk_allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .deny_idle = omap2_clkt_iclk_deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .find_companion = omap2_clk_dflt_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @clk: struct clk * being enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * The interface clocks on AM35xx IPSS reflects the clock idle status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * in the enable register itsel at a bit offset of 4 from the enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * bit. A value of 1 indicates that clock is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 *idlest_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 *idlest_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * am35xx_clk_find_companion - find companion clock to @clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @clk: struct clk * to find the companion clock of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @other_bit: u8 ** to return the companion clock bit shift in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Some clocks don't have companion clocks. For example, modules with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * only an interface clock (such as HECC) don't have a companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * clock. Right now, this code relies on the hardware exporting a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * in the correct companion register that indicates that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * nonexistent 'companion clock' is active. Future patches will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * associate this type of code with per-module data structures to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * avoid this issue, and remove the casts. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk_omap_reg *other_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 *other_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .find_idlest = am35xx_clk_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .find_companion = am35xx_clk_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @clk: struct clk * being enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * The IPSS target CM_IDLEST bit is at a different shift from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * and @idlest_bit. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 *idlest_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 *idlest_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) idlest_reg->offset &= ~0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) idlest_reg->offset |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *idlest_bit = AM35XX_ST_IPSS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *idlest_val = OMAP34XX_CM_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .allow_idle = omap2_clkt_iclk_allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .deny_idle = omap2_clkt_iclk_deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .find_idlest = am35xx_clk_ipss_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .find_companion = omap2_clk_dflt_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct ti_dt_clk omap3xxx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct ti_dt_clk omap3430es1_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct ti_dt_clk am35xx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const char *enable_init_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "sdrc_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "gpmc_fck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "omapctrl_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) OMAP3_SOC_AM35XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) OMAP3_SOC_OMAP3430_ES1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) OMAP3_SOC_OMAP3430_ES2_PLUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) OMAP3_SOC_OMAP3630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * omap3_clk_lock_dpll5 - locks DPLL5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Locks DPLL5 to a pre-defined frequency. This is required for proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * operation of USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void __init omap3_clk_lock_dpll5(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct clk *dpll5_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct clk *dpll5_m2_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Errata sprz319f advisory 2.1 documents a USB host clock drift issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * that can be worked around using specially crafted dpll5 settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * with a dpll5_m2 divider set to 8. Set the dpll5 rate to 8x the USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * host clock rate, its .set_rate handler() will detect that frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * and use the errata settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dpll5_clk = clk_get(NULL, "dpll5_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk_set_rate(dpll5_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_prepare_enable(dpll5_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Program dpll5_m2_clk divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_prepare_enable(dpll5_m2_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk_set_rate(dpll5_m2_clk, OMAP3_DPLL5_FREQ_FOR_USBHOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk_disable_unprepare(dpll5_m2_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk_disable_unprepare(dpll5_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int __init omap3xxx_dt_clk_init(int soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) soc_type == OMAP3_SOC_OMAP3430_ES1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ti_dt_clocks_register(omap3xxx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (soc_type == OMAP3_SOC_AM35XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ti_dt_clocks_register(am35xx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (soc_type == OMAP3_SOC_OMAP3430_ES1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ti_dt_clocks_register(omap3430es1_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) soc_type == OMAP3_SOC_OMAP3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) omap2_clk_enable_init_clocks(enable_init_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ARRAY_SIZE(enable_init_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (soc_type != OMAP3_SOC_OMAP3430_ES1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) omap3_clk_lock_dpll5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int __init omap3430_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int __init omap3630_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int __init am35xx_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags