^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AM33XX Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/clock/am3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const char * const am3_gpio1_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "clk-24mhz-clkctrl:0000:0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const char * const am3_gpio0_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "gpio0_dbclk_mux_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "sys_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "l3-aon-clkctrl:0000:19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "l3-aon-clkctrl:0000:30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "l3-aon-clkctrl:0000:20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .max_div = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "l3-aon-clkctrl:0000:22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .max_div = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const char * const am3_dbg_clka_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "dpll_core_m4_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x44e00038, am3_l4ls_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x44e0001c, am3_l3s_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x44e00024, am3_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x44e00120, am3_l4hs_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x44e00018, am3_lcdc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x44e00400, am3_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x44e00414, am3_l3_aon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x44e00600, am3_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x44e00800, am3_l4_rtc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x44e00900, am3_gfx_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct ti_dt_clk am33xx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char *enable_init_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "dpll_ddr_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "dpll_mpu_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "l3_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "l4hs_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "l4fw_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "l4ls_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Required for external peripherals like, Audio codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "clkout2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int __init am33xx_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct clk *clk1, *clk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ti_dt_clocks_register(am33xx_compat_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ti_dt_clocks_register(am33xx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) omap2_clk_enable_init_clocks(enable_init_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ARRAY_SIZE(enable_init_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * physically present, in such a case HWMOD enabling of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * clock would be failure with default parent. And timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * probe thinks clock is already enabled, this leads to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * crash upon accessing timer 3 & 6 registers in probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Fix by setting parent of both these timers to master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * oscillator clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk1 = clk_get_sys(NULL, "sys_clkin_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk2 = clk_get_sys(NULL, "timer3_fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_set_parent(clk2, clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk2 = clk_get_sys(NULL, "timer6_fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clk_set_parent(clk2, clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * the design/spec, so as a result, for example, timer which supposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * not expected by any use-case, so change WDT1 clock source to PRCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 32KHz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk1 = clk_get_sys(NULL, "wdt1_fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_set_parent(clk1, clk2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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