Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * AM33XX Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2013 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *     Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <dt-bindings/clock/am3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const char * const am3_gpio1_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	"l4_per_cm:clk:0138:0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{ AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{ AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{ AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{ AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{ AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{ AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{ AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{ AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const am3_gpio0_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	"gpio0_dbclk_mux_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	"sys_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	"l4_wkup_cm:clk:0010:19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	"l4_wkup_cm:clk:0010:30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	"l4_wkup_cm:clk:0010:20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.max_div = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	"l4_wkup_cm:clk:0010:22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.max_div = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const char * const am3_dbg_clka_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	"dpll_core_m4_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{ AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{ 0x44e00014, am3_l4_per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ 0x44e00404, am3_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{ 0x44e00604, am3_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ 0x44e00904, am3_gfx_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ti_dt_clk am33xx_compat_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };