Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * OMAP2 Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2013 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *     Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static struct ti_dt_clk omap2xxx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	DT_CLK(NULL, "func_32k_ck", "func_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	DT_CLK(NULL, "osc_ck", "osc_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	DT_CLK(NULL, "sys_ck", "sys_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	DT_CLK(NULL, "alt_ck", "alt_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	DT_CLK(NULL, "dpll_ck", "dpll_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	DT_CLK(NULL, "apll96_ck", "apll96_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	DT_CLK(NULL, "apll54_ck", "apll54_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	DT_CLK(NULL, "core_ck", "core_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	DT_CLK(NULL, "func_96m_ck", "func_96m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	DT_CLK(NULL, "func_48m_ck", "func_48m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	DT_CLK(NULL, "func_12m_ck", "func_12m_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	DT_CLK(NULL, "sys_clkout", "sys_clkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	DT_CLK(NULL, "emul_ck", "emul_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	DT_CLK(NULL, "mpu_ck", "mpu_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	DT_CLK(NULL, "dsp_fck", "dsp_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	DT_CLK(NULL, "gfx_ick", "gfx_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	DT_CLK("omapdss_dss", "ick", "dss_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	DT_CLK(NULL, "dss_ick", "dss_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	DT_CLK(NULL, "dss1_fck", "dss1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	DT_CLK(NULL, "dss2_fck", "dss2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	DT_CLK(NULL, "core_l3_ck", "core_l3_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	DT_CLK(NULL, "l4_ck", "l4_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	DT_CLK(NULL, "uart1_ick", "uart1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	DT_CLK(NULL, "uart1_fck", "uart1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	DT_CLK(NULL, "uart2_ick", "uart2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	DT_CLK(NULL, "uart2_fck", "uart2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	DT_CLK(NULL, "uart3_ick", "uart3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	DT_CLK(NULL, "uart3_fck", "uart3_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	DT_CLK(NULL, "gpios_ick", "gpios_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	DT_CLK(NULL, "gpios_fck", "gpios_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	DT_CLK("omap24xxcam", "fck", "cam_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	DT_CLK(NULL, "cam_fck", "cam_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	DT_CLK("omap24xxcam", "ick", "cam_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	DT_CLK(NULL, "cam_ick", "cam_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	DT_CLK(NULL, "wdt4_ick", "wdt4_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	DT_CLK(NULL, "wdt4_fck", "wdt4_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	DT_CLK(NULL, "mspro_ick", "mspro_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	DT_CLK(NULL, "mspro_fck", "mspro_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	DT_CLK(NULL, "fac_ick", "fac_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	DT_CLK(NULL, "fac_fck", "fac_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	DT_CLK(NULL, "hdq_ick", "hdq_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	DT_CLK(NULL, "hdq_fck", "hdq_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	DT_CLK(NULL, "sdma_fck", "sdma_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	DT_CLK(NULL, "sdma_ick", "sdma_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	DT_CLK(NULL, "des_ick", "des_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	DT_CLK("omap-sham", "ick", "sha_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	DT_CLK(NULL, "sha_ick", "sha_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	DT_CLK("omap_rng", "ick", "rng_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	DT_CLK(NULL, "rng_ick", "rng_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	DT_CLK("omap-aes", "ick", "aes_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	DT_CLK(NULL, "aes_ick", "aes_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	DT_CLK(NULL, "pka_ick", "pka_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	DT_CLK(NULL, "usb_fck", "usb_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	DT_CLK(NULL, "timer_ext_ck", "alt_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct ti_dt_clk omap2420_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	DT_CLK(NULL, "dsp_ick", "dsp_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	DT_CLK(NULL, "iva1_ifck", "iva1_ifck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	DT_CLK("mmci-omap.0", "ick", "mmc_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	DT_CLK(NULL, "mmc_ick", "mmc_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	DT_CLK("mmci-omap.0", "fck", "mmc_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	DT_CLK(NULL, "mmc_fck", "mmc_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	DT_CLK(NULL, "eac_ick", "eac_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	DT_CLK(NULL, "eac_fck", "eac_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	DT_CLK(NULL, "vlynq_ick", "vlynq_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	DT_CLK(NULL, "vlynq_fck", "vlynq_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	DT_CLK("musb-hdrc", "fck", "osc_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct ti_dt_clk omap2430_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	DT_CLK("twl", "fck", "osc_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	DT_CLK(NULL, "mdm_ick", "mdm_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	DT_CLK(NULL, "icr_ick", "icr_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	DT_CLK("musb-omap2430", "ick", "usbhs_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	DT_CLK(NULL, "usbhs_ick", "usbhs_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	DT_CLK(NULL, "gpio5_fck", "gpio5_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	{ .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char *enable_init_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	"apll96_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	"apll54_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	"sync_32k_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	"omapctrl_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	"gpmc_fck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	"sdrc_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	OMAP2_SOC_OMAP2420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	OMAP2_SOC_OMAP2430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int __init omap2xxx_dt_clk_init(int soc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ti_dt_clocks_register(omap2xxx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (soc_type == OMAP2_SOC_OMAP2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		ti_dt_clocks_register(omap2420_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		ti_dt_clocks_register(omap2430_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	omap2xxx_clkt_vps_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	omap2_clk_enable_init_clocks(enable_init_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				     ARRAY_SIZE(enable_init_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		(clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		(clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int __init omap2420_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2420);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int __init omap2430_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2430);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }