^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADPLL_PWRCTRL_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADPLL_PWRCTRL_PONIN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADPLL_PWRCTRL_PGOODIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADPLL_PWRCTRL_RET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADPLL_PWRCTRL_ISORET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADPLL_PWRCTRL_ISOSCAN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADPLL_PWRCTRL_OFFMODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADPLL_CLKCTRL_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADPLL_CLKCTRL_CLKDCOLDOEN 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADPLL_CLKCTRL_IDLE 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADPLL_CLKCTRL_CLKOUTEN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADPLL_CLKCTRL_ULOWCLKEN 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADPLL_CLKCTRL_M2PWDNZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ADPLL_CLKCTRL_TINITZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADPLL_TENABLE_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADPLL_TENABLEDIV_OFFSET 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADPLL_M2NDIV_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADPLL_M2NDIV_M2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADPLL_MN2DIV_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADPLL_MN2DIV_N2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ADPLL_FRACDIV_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ADPLL_FRACDIV_REGSD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADPLL_FRACDIV_FRACTIONALM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ADPLL_BWCTRL_OFFSET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ADPLL_BWCTRL_BWCONTROL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADPLL_BWCTRL_BW_INCR_DECRZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ADPLL_RESERVED_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADPLL_STATUS_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADPLL_STATUS_PONOUT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADPLL_STATUS_PGOODOUT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADPLL_STATUS_LDOPWDN 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADPLL_STATUS_RECAL_BSTATUS3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADPLL_STATUS_RECAL_OPPIN 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADPLL_STATUS_PHASELOCK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADPLL_STATUS_FREQLOCK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADPLL_STATUS_BYPASSACK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADPLL_STATUS_LOSSREF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADPLL_STATUS_CLKOUTENACK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ADPLL_STATUS_LOCK2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ADPLL_STATUS_M2CHANGEACK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADPLL_STATUS_HIGHJITTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ADPLL_STATUS_BYPASS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BIT(ADPLL_STATUS_FREQLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADPLL_M3DIV_M3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADPLL_M3DIV_M3_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADPLL_M3DIV_M3_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADPLL_RAMPCTRL_CLKRAMPRATE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX_ADPLL_INPUTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX_ADPLL_OUTPUTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ADPLL_MAX_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum ti_adpll_clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) TI_ADPLL_DCO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TI_ADPLL_DCO_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) TI_ADPLL_N2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TI_ADPLL_M2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) TI_ADPLL_M2_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TI_ADPLL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TI_ADPLL_HIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) TI_ADPLL_DIV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) TI_ADPLL_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) TI_ADPLL_CLKOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) TI_ADPLL_M3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum ti_adpll_inputs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) TI_ADPLL_CLKINP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) TI_ADPLL_CLKINPULOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) TI_ADPLL_CLKINPHIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum ti_adpll_s_outputs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) TI_ADPLL_S_DCOCLKLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) TI_ADPLL_S_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) TI_ADPLL_S_CLKOUTX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TI_ADPLL_S_CLKOUTHIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum ti_adpll_lj_outputs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TI_ADPLL_LJ_CLKDCOLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TI_ADPLL_LJ_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) TI_ADPLL_LJ_CLKOUTLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ti_adpll_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const bool is_type_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const int nr_max_inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const int nr_max_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const int output_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct ti_adpll_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk_lookup *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void (*unregister)(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ti_adpll_dco_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ti_adpll_clkout_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct ti_adpll_data *adpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ti_adpll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct ti_adpll_platform_data *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spinlock_t lock; /* For ADPLL shared register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char *parent_names[MAX_ADPLL_INPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct clk *parent_clocks[MAX_ADPLL_INPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ti_adpll_clock *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct clk_onecell_data outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct ti_adpll_dco_data dco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int output_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const char *postfix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (output_index >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) err = of_property_read_string_index(d->np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) output_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) d->pa, postfix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int index, int output_index, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void (*unregister)(struct clk *clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct clk_lookup *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const char *postfix = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) char con_id[ADPLL_MAX_CON_ID];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) d->clocks[index].clk = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) d->clocks[index].unregister = unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) postfix = strrchr(name, '.');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (postfix && strlen(postfix) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (strlen(postfix) > ADPLL_MAX_CON_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_warn(d->dev, "clock %s con_id lookup may fail\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) cl = clkdev_create(clock, con_id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) d->clocks[index].cl = cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_warn(d->dev, "no con_id for clock %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (output_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) d->outputs.clks[output_index] = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) d->outputs.clk_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int ti_adpll_init_divider(struct ti_adpll_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum ti_adpll_clocks index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int output_index, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk *parent_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 clk_divider_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const char *child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) child_name = ti_adpll_clk_get_name(d, output_index, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!child_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) parent_name = __clk_get_name(parent_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) clock = clk_register_divider(d->dev, child_name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg, shift, width, clk_divider_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(d->dev, "failed to register divider %s: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) name, PTR_ERR(clock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_unregister_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int ti_adpll_init_mux(struct ti_adpll_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum ti_adpll_clocks index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) char *name, struct clk *clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk *clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) const char *child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const char *parents[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!child_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) parents[0] = __clk_get_name(clk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) parents[1] = __clk_get_name(clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reg, shift, 1, 0, &d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(d->dev, "failed to register mux %s: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) name, PTR_ERR(clock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk_unregister_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int ti_adpll_init_gate(struct ti_adpll_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) enum ti_adpll_clocks index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int output_index, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct clk *parent_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 clk_gate_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const char *child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) child_name = ti_adpll_clk_get_name(d, output_index, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!child_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) parent_name = __clk_get_name(parent_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clock = clk_register_gate(d->dev, child_name, parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg, bit_idx, clk_gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) &d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(d->dev, "failed to register gate %s: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) name, PTR_ERR(clock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) clk_unregister_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) enum ti_adpll_clocks index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct clk *parent_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) const char *child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!child_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) parent_name = __clk_get_name(parent_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (IS_ERR(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) clk_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_lock_irqsave(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) v |= BIT(ADPLL_CLKCTRL_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_unlock_irqrestore(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) v &= ~BIT(ADPLL_CLKCTRL_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spin_unlock_irqrestore(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return v & BIT(ADPLL_STATUS_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Locked and bypass are not actually mutually exclusive: if you only care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static bool ti_adpll_is_locked(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ti_adpll_wait_lock(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int retries = ADPLL_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ti_adpll_is_locked(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) usleep_range(200, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } while (retries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(d->dev, "pll failed to lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int ti_adpll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct ti_adpll_dco_data *dco = to_dco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct ti_adpll_data *d = to_adpll(dco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ti_adpll_clear_idle_bypass(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ti_adpll_wait_lock(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void ti_adpll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct ti_adpll_dco_data *dco = to_dco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct ti_adpll_data *d = to_adpll(dco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ti_adpll_set_idle_bypass(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int ti_adpll_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct ti_adpll_dco_data *dco = to_dco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct ti_adpll_data *d = to_adpll(dco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ti_adpll_is_locked(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Note that the DCO clock is never subject to bypass: if the PLL is off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * dcoclk is low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct ti_adpll_dco_data *dco = to_dco(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct ti_adpll_data *d = to_adpll(dco);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 frac_m, divider, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ti_adpll_clock_is_bypass(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_lock_irqsave(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) rate += frac_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rate *= parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_unlock_irqrestore(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) do_div(rate, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (d->c->is_type_s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rate *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* PLL parent is always clkinp, bypass only affects the children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static u8 ti_adpll_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct clk_ops ti_adpll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .prepare = ti_adpll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .unprepare = ti_adpll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .is_prepared = ti_adpll_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .recalc_rate = ti_adpll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .get_parent = ti_adpll_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int ti_adpll_init_dco(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const char *postfix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int width, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) d->outputs.clks = devm_kcalloc(d->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MAX_ADPLL_OUTPUTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sizeof(struct clk *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!d->outputs.clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (d->c->output_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) postfix = "dco";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) postfix = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) init.parent_names = d->parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) init.num_parents = d->c->nr_max_inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) init.ops = &ti_adpll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) init.flags = CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) d->dco.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (d->c->is_type_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) width = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Internal input clock divider N2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) d->parent_clocks[TI_ADPLL_CLKINP],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) d->regs + ADPLL_MN2DIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ADPLL_MN2DIV_N2, width, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clock = devm_clk_register(d->dev, &d->dco.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (IS_ERR(clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) init.name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int ti_adpll_clkout_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct ti_adpll_clkout_data *co = to_clkout(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct clk_hw *gate_hw = &co->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return clk_gate_ops.enable(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void ti_adpll_clkout_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ti_adpll_clkout_data *co = to_clkout(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct clk_hw *gate_hw = &co->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clk_gate_ops.disable(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct ti_adpll_clkout_data *co = to_clkout(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct clk_hw *gate_hw = &co->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) __clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return clk_gate_ops.is_enabled(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ti_adpll_clkout_data *co = to_clkout(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct ti_adpll_data *d = co->adpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ti_adpll_clock_is_bypass(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int ti_adpll_init_clkout(struct ti_adpll_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) enum ti_adpll_clocks index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int output_index, int gate_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) char *name, struct clk *clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct clk *clk1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct ti_adpll_clkout_data *co;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct clk_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) const char *child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!co)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) co->adpll = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) err = of_property_read_string_index(d->np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) output_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &child_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) init.name = child_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) co->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) parent_names[0] = __clk_get_name(clk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) parent_names[1] = __clk_get_name(clk1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) init.num_parents = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ops->get_parent = ti_adpll_clkout_get_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ops->determine_rate = __clk_mux_determine_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (gate_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) co->gate.lock = &d->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) co->gate.bit_idx = gate_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ops->enable = ti_adpll_clkout_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ops->disable = ti_adpll_clkout_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ops->is_enabled = ti_adpll_clkout_is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) clock = devm_clk_register(d->dev, &co->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_err(d->dev, "failed to register output %s: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) name, PTR_ERR(clock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!d->c->is_type_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Internal mux, sources from divider N2 or clkinpulow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) d->clocks[TI_ADPLL_N2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) d->parent_clocks[TI_ADPLL_CLKINPULOW],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) d->regs + ADPLL_CLKCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ADPLL_CLKCTRL_ULOWCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Internal divider M2, sources DCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) d->clocks[TI_ADPLL_DCO].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) d->regs + ADPLL_M2NDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ADPLL_M2NDIV_M2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CLK_DIVIDER_ONE_BASED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Internal fixed divider, after M2 before clkout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) d->clocks[TI_ADPLL_M2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Output clkout with a mux and gate, sources from div2 or bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ADPLL_CLKCTRL_CLKOUTEN, "clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) d->clocks[TI_ADPLL_DIV2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) d->clocks[TI_ADPLL_BYPASS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "clkout2", d->clocks[TI_ADPLL_M2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) d->clocks[TI_ADPLL_BYPASS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Internal mux, sources from DCO and clkinphif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) d->clocks[TI_ADPLL_DCO].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) d->parent_clocks[TI_ADPLL_CLKINPHIF],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) d->regs + ADPLL_CLKCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ADPLL_CLKINPHIFSEL_ADPLL_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Output clkouthif with a divider M3, sources from hif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) d->clocks[TI_ADPLL_HIF].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) d->regs + ADPLL_M3DIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ADPLL_M3DIV_M3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ADPLL_M3DIV_M3_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) CLK_DIVIDER_ONE_BASED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Output clock dcoclkldo is the DCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (d->c->is_type_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Output clkdcoldo, gated output of DCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) d->regs + ADPLL_CLKCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Internal divider M2, sources from DCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "m2", d->clocks[TI_ADPLL_DCO].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) d->regs + ADPLL_M2NDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ADPLL_M2NDIV_M2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) CLK_DIVIDER_ONE_BASED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Output clkoutldo, gated output of M2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) d->regs + ADPLL_CLKCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Internal mux, sources from divider N2 or clkinpulow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) d->clocks[TI_ADPLL_N2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) d->parent_clocks[TI_ADPLL_CLKINPULOW],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) d->regs + ADPLL_CLKCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ADPLL_CLKCTRL_ULOWCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Output clkout, sources M2 or bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ADPLL_CLKCTRL_CLKOUTEN, "clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) d->clocks[TI_ADPLL_M2].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) d->clocks[TI_ADPLL_BYPASS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static void ti_adpll_free_resources(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) for (i = TI_ADPLL_M3; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct ti_adpll_clock *ac = &d->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!ac || IS_ERR_OR_NULL(ac->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ac->cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clkdev_drop(ac->cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ac->unregister)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ac->unregister(ac->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* MPU PLL manages the lock register for all PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void ti_adpll_unlock_all(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) v = readl_relaxed(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int ti_adpll_init_registers(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int register_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (d->c->is_type_s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) register_offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int ti_adpll_init_inputs(struct ti_adpll_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) const char *error = "need at least %i inputs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int nr_inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) nr_inputs = of_clk_get_parent_count(d->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (nr_inputs < d->c->nr_max_inputs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_err(d->dev, error, nr_inputs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clock = devm_clk_get(d->dev, d->parent_names[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(d->dev, "could not get clkinp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) d->parent_clocks[TI_ADPLL_CLKINP] = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) clock = devm_clk_get(d->dev, d->parent_names[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(d->dev, "could not get clkinpulow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (d->c->is_type_s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) clock = devm_clk_get(d->dev, d->parent_names[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (IS_ERR(clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_err(d->dev, "could not get clkinphif clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return PTR_ERR(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const struct ti_adpll_platform_data ti_adpll_type_s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .is_type_s = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .nr_max_inputs = MAX_ADPLL_INPUTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .nr_max_outputs = MAX_ADPLL_OUTPUTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .output_index = TI_ADPLL_S_DCOCLKLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const struct ti_adpll_platform_data ti_adpll_type_lj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .is_type_s = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .output_index = -EINVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct of_device_id ti_adpll_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) MODULE_DEVICE_TABLE(of, ti_adpll_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int ti_adpll_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) const struct ti_adpll_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct ti_adpll_data *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) match = of_match_device(ti_adpll_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) d->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) d->np = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) d->c = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev_set_drvdata(d->dev, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) spin_lock_init(&d->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) d->pa = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) d->iobase = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (IS_ERR(d->iobase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_err(dev, "could not get IO base: %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PTR_ERR(d->iobase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return PTR_ERR(d->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) err = ti_adpll_init_registers(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) err = ti_adpll_init_inputs(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) d->clocks = devm_kcalloc(d->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) TI_ADPLL_NR_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) sizeof(struct ti_adpll_clock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!d->clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) err = ti_adpll_init_dco(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(dev, "could not register dco: %i\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) err = ti_adpll_init_children_adpll_s(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) err = ti_adpll_init_children_adpll_lj(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ti_adpll_free_resources(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int ti_adpll_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ti_adpll_free_resources(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static struct platform_driver ti_adpll_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .name = "ti-adpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .of_match_table = ti_adpll_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .probe = ti_adpll_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .remove = ti_adpll_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int __init ti_adpll_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return platform_driver_register(&ti_adpll_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) core_initcall(ti_adpll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static void __exit ti_adpll_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) platform_driver_unregister(&ti_adpll_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) module_exit(ti_adpll_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MODULE_ALIAS("platform:dm814-adpll-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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