^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __TEGRA_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __TEGRA_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_OUT_ENB_L 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_OUT_ENB_H 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_OUT_ENB_U 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_OUT_ENB_V 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_OUT_ENB_W 0x364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_OUT_ENB_X 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_OUT_ENB_Y 0x298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_ENB_PLLP_OUT_CPU BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_OUT_ENB_SET_L 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_OUT_ENB_CLR_L 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_OUT_ENB_SET_H 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_OUT_ENB_CLR_H 0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_OUT_ENB_SET_U 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_OUT_ENB_CLR_U 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_OUT_ENB_SET_V 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_OUT_ENB_CLR_V 0x444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_OUT_ENB_SET_W 0x448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_OUT_ENB_CLR_W 0x44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_OUT_ENB_SET_X 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_OUT_ENB_CLR_X 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_OUT_ENB_SET_Y 0x29c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_OUT_ENB_CLR_Y 0x2a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RST_DEVICES_L 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RST_DEVICES_H 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RST_DEVICES_U 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RST_DEVICES_V 0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RST_DEVICES_W 0x35C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RST_DEVICES_X 0x28C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RST_DEVICES_Y 0x2a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RST_DEVICES_SET_L 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RST_DEVICES_CLR_L 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RST_DEVICES_SET_H 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RST_DEVICES_CLR_H 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RST_DEVICES_SET_U 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RST_DEVICES_CLR_U 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RST_DEVICES_SET_V 0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RST_DEVICES_CLR_V 0x434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RST_DEVICES_SET_W 0x438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RST_DEVICES_CLR_W 0x43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RST_DEVICES_SET_X 0x290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RST_DEVICES_CLR_X 0x294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RST_DEVICES_SET_Y 0x2a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RST_DEVICES_CLR_Y 0x2ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * any accidental write of 1 to these bits can cause PSLVERR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * So below are the valid mask defines for each CLK_OUT_ENB register used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * turn ON only the valid clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA210_CLK_ENB_VLD_MSK_L 0xdcd7dff9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA210_CLK_ENB_VLD_MSK_H 0x87d1f3e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA210_CLK_ENB_VLD_MSK_U 0xf3fed3fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA210_CLK_ENB_VLD_MSK_V 0xffc18cfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA210_CLK_ENB_VLD_MSK_W 0x793fb7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA210_CLK_ENB_VLD_MSK_X 0x3fe66fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA210_CLK_ENB_VLD_MSK_Y 0xfc1fc7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * struct tegra_clk_sync_source - external clock source from codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @rate: input frequency from source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @max_rate: max rate allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct tegra_clk_sync_source {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define to_clk_sync_source(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) container_of(_hw, struct tegra_clk_sync_source, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern const struct clk_ops tegra_clk_sync_source_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern int *periph_clk_enb_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk *tegra_clk_register_sync_source(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct tegra_clk_frac_div - fractional divider clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @reg: register containing divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @shift: shift to the divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @width: width of the divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @frac_width: width of the fractional bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @lock: register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * flag indicates that this divider is for fixed rate PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * fraction bit is set. This flags indicates to calculate divider for which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * fracton bit will be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * set when divider value is not 0. This flags indicates that the divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * is for UART module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct tegra_clk_frac_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 frac_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA_DIVIDER_ROUND_UP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA_DIVIDER_FIXED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA_DIVIDER_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA_DIVIDER_UART BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern const struct clk_ops tegra_clk_frac_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct clk *tegra_clk_register_divider(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char *parent_name, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 frac_width, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __iomem *reg, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Tegra PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * In general, there are 3 requirements for each PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * that SW needs to be comply with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * (1) Input frequency range (REF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * (2) Comparison frequency range (CF). CF = REF/DIVM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * (3) VCO frequency range (VCO). VCO = CF * DIVN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * The final PLL output frequency (FO) = VCO >> DIVP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * struct tegra_clk_pll_freq_table - PLL frequecy table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @input_rate: input rate from source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @output_rate: output rate from PLL for the input rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @n: feedback divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @m: input divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @p: post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @cpcon: charge pump current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @sdm_data: fraction divider setting (0 = disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct tegra_clk_pll_freq_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long output_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 cpcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 sdm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * struct pdiv_map - map post divider to hw value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @pdiv: post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @hw_val: value to be written to the PLL hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct pdiv_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 hw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * struct div_nmp - offset and width of m,n and p fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @divn_shift: shift to the feedback divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @divn_width: width of the feedback divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @divm_shift: shift to the input divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @divm_width: width of the input divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @divp_shift: shift to the post divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @divp_width: width of the post divider bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @override_divn_shift: shift to the feedback divider bitfield in override reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @override_divm_shift: shift to the input divider bitfield in override reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @override_divp_shift: shift to the post divider bitfield in override reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct div_nmp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 divn_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 divn_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 divm_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 divm_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 divp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 divp_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 override_divn_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 override_divm_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 override_divp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MAX_PLL_MISC_REG_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct tegra_clk_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * struct tegra_clk_pll_params - PLL parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @input_min: Minimum input frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @input_max: Maximum input frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @cf_min: Minimum comparison frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @cf_max: Maximum comparison frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @vco_min: Minimum VCO frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @vco_max: Maximum VCO frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @base_reg: PLL base reg offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @misc_reg: PLL misc reg offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @lock_reg: PLL lock reg offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @lock_mask: Bitmask for PLL lock status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @lock_enable_bit_idx: Bit index to enable PLL lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @iddq_reg: PLL IDDQ register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @iddq_bit_idx: Bit index to enable PLL IDDQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @reset_reg: Register offset of where RESET bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @reset_bit_idx: Shift of reset bit in reset_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @sdm_din_reg: Register offset where SDM settings are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @sdm_din_mask: Mask of SDM divider bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @sdm_ctrl_reg: Register offset where SDM enable is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @sdm_ctrl_en_mask: Mask of SDM enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @ssc_ctrl_reg: Register offset where SSC settings are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @ssc_ctrl_en_mask: Mask of SSC enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @aux_reg: AUX register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @dyn_ramp_reg: Dynamic ramp control register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @ext_misc_reg: Miscellaneous control register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @pmc_divp_reg: p divider PMC override register offset (PLLM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @flags: PLL flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @stepa_shift: Dynamic ramp step A field shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @stepb_shift: Dynamic ramp step B field shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @lock_delay: Delay in us if PLL lock is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @max_p: maximum value for the p divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @defaults_set: Boolean signaling all reg defaults for PLL set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @pdiv_tohw: mapping of p divider to register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @div_nmp: offsets and widths on n, m and p fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @freq_table: array of frequencies supported by PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @fixed_rate: PLL rate if it is fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @mdiv_default: Default value for fixed mdiv for this PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @round_p_to_pdiv: Callback used to round p to the closed pdiv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @set_gain: Callback to adjust N div for SDM enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * PLL's based on fractional divider value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @calc_rate: Callback used to change how out of table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * rates (dividers and multipler) are calculated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @adjust_vco: Callback to adjust the programming range of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * divider range (if SDM is present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @set_defaults: Callback which will try to initialize PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * registers to sane default values. This is first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * tried during PLL registration, but if the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * is already enabled, it will be done the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * time the rate is changed while the PLL is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @dyn_ramp: Callback which can be used to define a custom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * dynamic ramp function for a given PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @pre_rate_change: Callback which is invoked just before changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * PLL's rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @post_rate_change: Callback which is invoked right after changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * PLL's rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * PLL locking. If not set it will use lock_delay value to wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * to be programmed to change output frequency of the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * to be programmed to change output frequency of the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * to be programmed to change output frequency of the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * that it is PLLU and invert post divider value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * TEGRA_PLLM - PLLM has additional override settings in PMC. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * flag indicates that it is PLLM and use override settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * TEGRA_PLL_FIXED - We are not supposed to change output frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * of some plls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * base register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * TEGRA_PLL_BYPASS - PLL has bypass bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * it may be more accurate (especially if SDM present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * flag indicated that it is PLLMB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct tegra_clk_pll_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long input_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long input_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long cf_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long cf_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned long vco_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long vco_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 misc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 lock_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 lock_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 lock_enable_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 iddq_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 iddq_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 reset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 reset_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 sdm_din_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 sdm_din_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 sdm_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 sdm_ctrl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 ssc_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 ssc_ctrl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 aux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 dyn_ramp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 pmc_divnm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 pmc_divp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int stepa_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int stepb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int lock_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int max_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bool defaults_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const struct pdiv_map *pdiv_tohw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct div_nmp *div_nmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct tegra_clk_pll_freq_table *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u16 mdiv_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int (*calc_rate)(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long rate, unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void (*set_defaults)(struct tegra_clk_pll *pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int (*dyn_ramp)(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct tegra_clk_pll_freq_table *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int (*pre_rate_change)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void (*post_rate_change)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TEGRA_PLL_USE_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TEGRA_PLL_HAS_CPCON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TEGRA_PLL_SET_LFCON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TEGRA_PLL_SET_DCCON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define TEGRA_PLLU BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TEGRA_PLLM BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TEGRA_PLL_FIXED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TEGRA_PLLE_CONFIGURE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TEGRA_PLL_LOCK_MISC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TEGRA_PLL_BYPASS BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TEGRA_MDIV_NEW BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TEGRA_PLLMB BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TEGRA_PLL_VCO_OUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * struct tegra_clk_pll - Tegra PLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @hw: handle between common and hardware-specifix interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * @clk_base: address of CAR controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @pmc: address of PMC, required to read override bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @lock: register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @params: PLL parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct tegra_clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void __iomem *pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct tegra_clk_pll_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * struct tegra_audio_clk_info - Tegra Audio Clk Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @name: name for the audio pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @pll_params: pll_params for audio pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * @clk_id: clk_ids for the audio pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @parent: name of the parent of the audio pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct tegra_audio_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct tegra_clk_pll_params *pll_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) extern const struct clk_ops tegra_clk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) extern const struct clk_ops tegra_clk_plle_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned long flags, struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long flags, struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spinlock_t *lock, unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct clk *tegra_clk_register_pllre_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const char *parent_name, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void __iomem *pmc, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spinlock_t *lock, unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct clk *tegra_clk_register_plle_tegra114(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct clk *tegra_clk_register_plle_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct clk *tegra_clk_register_pllc_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const char *parent_name, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void __iomem *pmc, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct clk *tegra_clk_register_pllss_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const char *parent_name, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct clk *tegra_clk_register_pllu_tegra114(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct clk *tegra_clk_register_pllu_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * struct tegra_clk_pll_out - PLL divider down clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * @reg: register containing the PLL divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * @enb_bit_idx: bit to enable/disable PLL divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @rst_bit_idx: bit to reset PLL divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @lock: register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct tegra_clk_pll_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 enb_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 rst_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) extern const struct clk_ops tegra_clk_pll_out_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct clk *tegra_clk_register_pll_out(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * struct tegra_clk_periph_regs - Registers controlling peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * @enb_reg: read the enable status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * @enb_set_reg: write 1 to enable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @enb_clr_reg: write 1 to disable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @rst_reg: read the reset status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @rst_set_reg: write 1 to assert the reset of peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * @rst_clr_reg: write 1 to deassert the reset of peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct tegra_clk_periph_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 enb_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 enb_set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 enb_clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 rst_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 rst_set_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 rst_clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * struct tegra_clk_periph_gate - peripheral gate clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * @magic: magic number to validate type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @clk_base: address of CAR controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @regs: Registers to control the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @clk_num: Clock number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @enable_refcnt: array to maintain reference count of the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * for this module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * after clock enable and driver for the module is responsible for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * doing reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * bus to flush the write operation in apb bus. This flag indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * that this peripheral is in apb bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct tegra_clk_periph_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int *enable_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) const struct tegra_clk_periph_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define to_clk_periph_gate(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) container_of(_hw, struct tegra_clk_periph_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define TEGRA_PERIPH_NO_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define TEGRA_PERIPH_ON_APB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define TEGRA_PERIPH_WAR_1005168 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define TEGRA_PERIPH_NO_DIV BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define TEGRA_PERIPH_NO_GATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) extern const struct clk_ops tegra_clk_periph_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct clk *tegra_clk_register_periph_gate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const char *parent_name, u8 gate_flags, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned long flags, int clk_num, int *enable_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct tegra_clk_periph_fixed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const struct tegra_clk_periph_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct clk *tegra_clk_register_periph_fixed(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * struct clk-periph - peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * @magic: magic number to validate type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * @mux: mux clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * @divider: divider clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * @gate: gate clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @mux_ops: mux clock ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @div_ops: divider clock ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @gate_ops: gate clock ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct tegra_clk_periph {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct tegra_clk_frac_div divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct tegra_clk_periph_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) const struct clk_ops *mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const struct clk_ops *div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) const struct clk_ops *gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define TEGRA_CLK_PERIPH_MAGIC 0x18221223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) extern const struct clk_ops tegra_clk_periph_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct clk *tegra_clk_register_periph(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) const char * const *parent_names, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct tegra_clk_periph *periph, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 offset, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct clk *tegra_clk_register_periph_nodiv(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const char * const *parent_names, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct tegra_clk_periph *periph, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) _div_shift, _div_width, _div_frac_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) _div_flags, _clk_num,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) _gate_flags, _table, _lock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .mux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .flags = _mux_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .shift = _mux_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .mask = _mux_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .lock = _lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .divider = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .flags = _div_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .shift = _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .width = _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .frac_width = _div_frac_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .lock = _lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .gate = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .flags = _gate_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .clk_num = _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .mux_ops = &clk_mux_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .div_ops = &tegra_clk_frac_div_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .gate_ops = &tegra_clk_periph_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct tegra_periph_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) const char *const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct tegra_clk_periph periph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) const char *con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) const char *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) _mux_shift, _mux_mask, _mux_flags, _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) _div_width, _div_frac_width, _div_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) _clk_num, _gate_flags, _clk_id, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) _flags, _lock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .clk_id = _clk_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .p.parent_names = _parent_names, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .num_parents = ARRAY_SIZE(_parent_names), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) _mux_flags, _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) _div_width, _div_frac_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) _div_flags, _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) _gate_flags, _table, _lock), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .con_id = _con_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .dev_id = _dev_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .flags = _flags \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) _mux_shift, _mux_width, _mux_flags, _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) _div_width, _div_frac_width, _div_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) _div_shift, _div_width, _div_frac_width, _div_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) _clk_num, _gate_flags, _clk_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) NULL, 0, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct tegra_periph_init_data *init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * struct clk_super_mux - super clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * @reg: register controlling multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * @width: width of the multiplexer bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * @div2_index: bit controlling divide-by-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * @pllx_index: PLLX index in the parent list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * @lock: register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * that this is LP cluster clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * super mux parent using PLLP branches. To use PLLP branches to CPU, need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * to configure additional bit PLLP_OUT_CPU in the clock registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * clocks, it only has a clock-skipper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct tegra_clk_super_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct tegra_clk_frac_div frac_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const struct clk_ops *div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u8 div2_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 pllx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define TEGRA_DIVIDER_2 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define TEGRA210_CPU_CLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define TEGRA20_SUPER_CLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) extern const struct clk_ops tegra_clk_super_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct clk *tegra_clk_register_super_mux(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) const char **parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unsigned long flags, void __iomem *reg, u8 clk_super_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct clk *tegra_clk_register_super_clk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) const char * const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned long flags, void __iomem *reg, u8 clk_super_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct clk *tegra_clk_register_super_cclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) const char * const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) unsigned long flags, void __iomem *reg, u8 clk_super_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int tegra_cclk_pre_pllx_rate_change(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) void tegra_cclk_post_pllx_rate_change(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * @reg: register controlling mux and divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * @lock: optional register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * @gate: gate clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * @gate_ops: gate clock ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct tegra_sdmmc_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) const struct clk_ops *gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct tegra_clk_periph_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u8 div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned long flags, void *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * struct clk_init_table - clock initialization table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * @clk_id: clock id as mentioned in device tree bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * @parent_id: parent clock id as mentioned in device tree bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * @rate: rate to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * @state: enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct tegra_clk_init_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned int parent_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * struct clk_duplicate - duplicate clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * @clk_id: clock id as mentioned in device tree bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * @lookup: duplicate lookup entry for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct tegra_clk_duplicate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct clk_lookup lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .clk_id = _clk_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .lookup = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .dev_id = _dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .con_id = _con, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct tegra_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int dt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) bool present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct tegra_devclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int dt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) char *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) char *con_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int (*deassert)(unsigned long));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) void tegra_init_from_table(struct tegra_clk_init_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct clk *clks[], int clk_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct clk *clks[], int clk_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) const struct tegra_clk_periph_regs *get_reg_bank(int clkid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) void tegra_audio_clk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) void __iomem *pmc_base, struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct tegra_audio_clk_info *audio_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned int num_plls, unsigned long sync_max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct tegra_clk_pll_params *pll_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) unsigned long *input_freqs, unsigned int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) unsigned int clk_m_div, unsigned long *osc_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned long *pll_ref_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) void tegra_super_clk_gen4_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) void __iomem *pmc_base, struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct tegra_clk_pll_params *pll_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) void tegra_super_clk_gen5_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) void __iomem *pmc_base, struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct tegra_clk_pll_params *pll_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #ifdef CONFIG_TEGRA124_EMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static inline struct clk *tegra_clk_register_emc(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void tegra114_clock_tune_cpu_trimmers_high(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) void tegra114_clock_tune_cpu_trimmers_low(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) void tegra114_clock_tune_cpu_trimmers_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) void tegra114_clock_assert_dfll_dvco_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) void tegra114_clock_deassert_dfll_dvco_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) typedef void (*tegra_clk_apply_init_table_func)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u8 frac_width, u8 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) void tegra_clk_osc_resume(void __iomem *clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) void tegra_clk_set_pllp_out_cpu(bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) void tegra_clk_periph_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) void tegra_clk_periph_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Combined read fence with delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define fence_udelay(delay, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) readl(reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) udelay(delay); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct clk *tegra210_clk_register_emc(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) void __iomem *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #endif /* TEGRA_CLK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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