Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Global data of Tegra CPU CAR ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static struct tegra_cpu_car_ops dummy_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) int *periph_clk_enb_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static int periph_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static u32 *periph_state_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static int clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Handlers for SoC-specific reset lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int (*special_reset_assert)(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int (*special_reset_deassert)(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static unsigned int num_special_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static const struct tegra_clk_periph_regs periph_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.enb_reg = CLK_OUT_ENB_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.enb_set_reg = CLK_OUT_ENB_SET_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.enb_clr_reg = CLK_OUT_ENB_CLR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.rst_reg = RST_DEVICES_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.rst_set_reg = RST_DEVICES_SET_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.rst_clr_reg = RST_DEVICES_CLR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.enb_reg = CLK_OUT_ENB_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.enb_set_reg = CLK_OUT_ENB_SET_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.enb_clr_reg = CLK_OUT_ENB_CLR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.rst_reg = RST_DEVICES_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.rst_set_reg = RST_DEVICES_SET_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.rst_clr_reg = RST_DEVICES_CLR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.enb_reg = CLK_OUT_ENB_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.enb_set_reg = CLK_OUT_ENB_SET_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.enb_clr_reg = CLK_OUT_ENB_CLR_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.rst_reg = RST_DEVICES_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.rst_set_reg = RST_DEVICES_SET_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.rst_clr_reg = RST_DEVICES_CLR_U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.enb_reg = CLK_OUT_ENB_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.enb_set_reg = CLK_OUT_ENB_SET_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.enb_clr_reg = CLK_OUT_ENB_CLR_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.rst_reg = RST_DEVICES_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.rst_set_reg = RST_DEVICES_SET_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.rst_clr_reg = RST_DEVICES_CLR_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.enb_reg = CLK_OUT_ENB_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.enb_set_reg = CLK_OUT_ENB_SET_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.enb_clr_reg = CLK_OUT_ENB_CLR_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.rst_reg = RST_DEVICES_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.rst_set_reg = RST_DEVICES_SET_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.rst_clr_reg = RST_DEVICES_CLR_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.enb_reg = CLK_OUT_ENB_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.enb_set_reg = CLK_OUT_ENB_SET_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.enb_clr_reg = CLK_OUT_ENB_CLR_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.rst_reg = RST_DEVICES_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.rst_set_reg = RST_DEVICES_SET_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.rst_clr_reg = RST_DEVICES_CLR_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.enb_reg = CLK_OUT_ENB_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.enb_set_reg = CLK_OUT_ENB_SET_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.enb_clr_reg = CLK_OUT_ENB_CLR_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.rst_reg = RST_DEVICES_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.rst_set_reg = RST_DEVICES_SET_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.rst_clr_reg = RST_DEVICES_CLR_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * If peripheral is on the APB bus then we must read the APB bus to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * flush the write operation in apb bus. This will avoid peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * access after disabling clock. Since the reset driver has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * knowledge of which reset IDs represent which devices, simply do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * this all the time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tegra_read_chipid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (id < periph_banks * 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		writel_relaxed(BIT(id % 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			       clk_base + periph_regs[id / 32].rst_set_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	} else if (id < periph_banks * 32 + num_special_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return special_reset_assert(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (id < periph_banks * 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		writel_relaxed(BIT(id % 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			       clk_base + periph_regs[id / 32].rst_clr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	} else if (id < periph_banks * 32 + num_special_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return special_reset_deassert(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int tegra_clk_rst_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	err = tegra_clk_rst_assert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return tegra_clk_rst_deassert(rcdev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int reg_bank = clkid / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (reg_bank < periph_banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return &periph_regs[reg_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void tegra_clk_set_pllp_out_cpu(bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		val |= CLK_ENB_PLLP_OUT_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		val &= ~CLK_ENB_PLLP_OUT_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void tegra_clk_periph_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	unsigned int i, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	for (i = 0; i < periph_banks; i++, idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		periph_state_ctx[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			readl_relaxed(clk_base + periph_regs[i].enb_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	for (i = 0; i < periph_banks; i++, idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		periph_state_ctx[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			readl_relaxed(clk_base + periph_regs[i].rst_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void tegra_clk_periph_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned int i, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	for (i = 0; i < periph_banks; i++, idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		writel_relaxed(periph_state_ctx[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			       clk_base + periph_regs[i].enb_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * All non-boot peripherals will be in reset state on resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * Wait for 5us of reset propagation delay before de-asserting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * the peripherals based on the saved context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	fence_udelay(5, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	for (i = 0; i < periph_banks; i++, idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		writel_relaxed(periph_state_ctx[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			       clk_base + periph_regs[i].rst_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	fence_udelay(2, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int tegra_clk_periph_ctx_init(int banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!periph_state_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	clk_base = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	periph_clk_enb_refcnt = kcalloc(32 * banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					sizeof(*periph_clk_enb_refcnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (!periph_clk_enb_refcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	periph_banks = banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		kfree(periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	clk_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (tegra_clk_periph_ctx_init(banks)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			kfree(periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			kfree(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				struct clk *clks[], int clk_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (; dup_list->clk_id < clk_max; dup_list++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		clk = clks[dup_list->clk_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		dup_list->lookup.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		clkdev_add(&dup_list->lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				  struct clk *clks[], int clk_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	for (; tbl->clk_id < clk_max; tbl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		clk = clks[tbl->clk_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		if (IS_ERR_OR_NULL(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			pr_err("%s: invalid entry %ld in clks array for id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			       __func__, PTR_ERR(clk), tbl->clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		if (tbl->parent_id < clk_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			struct clk *parent = clks[tbl->parent_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			if (clk_set_parent(clk, parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				pr_err("%s: Failed to set parent %s of %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				       __func__, __clk_get_name(parent),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				       __clk_get_name(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (tbl->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			if (clk_set_rate(clk, tbl->rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				pr_err("%s: Failed to set rate %lu of %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				       __func__, tbl->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				       __clk_get_name(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		if (tbl->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			if (clk_prepare_enable(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				pr_err("%s: Failed to enable %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				       __clk_get_name(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct reset_control_ops rst_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.assert = tegra_clk_rst_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.deassert = tegra_clk_rst_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.reset = tegra_clk_rst_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct reset_controller_dev rst_ctlr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.ops = &rst_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.of_reset_n_cells = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void __init tegra_add_of_provider(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				  void *clk_src_onecell_get)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	for (i = 0; i < clk_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		if (IS_ERR(clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			pr_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			    ("Tegra clk %d: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			     i, PTR_ERR(clks[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (!clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			clks[i] = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	clk_data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	clk_data.clk_num = clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	of_clk_add_provider(np, clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	rst_ctlr.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	reset_controller_register(&rst_ctlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void __init tegra_init_special_resets(unsigned int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				      int (*assert)(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				      int (*deassert)(unsigned long))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	num_special_reset = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	special_reset_assert = assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	special_reset_deassert = deassert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	for (i = 0; i < num; i++, dev_clks++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				dev_clks->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	for (i = 0; i < clk_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if (!IS_ERR_OR_NULL(clks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				"tegra-clk-debug");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct clk ** __init tegra_lookup_dt_id(int clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 					struct tegra_clk *tegra_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (tegra_clk[clk_id].present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return &clks[tegra_clk[clk_id].dt_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int __init tegra_clocks_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (!tegra_clk_apply_init_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	tegra_clk_apply_init_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) arch_initcall(tegra_clocks_apply_init_table);