Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define div_mask(w) ((1 << (w)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		 u8 frac_width, u8 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	u64 divider_ux1 = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	int mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	mul = 1 << frac_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	if (!(flags & TEGRA_DIVIDER_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		divider_ux1 *= mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	if (flags & TEGRA_DIVIDER_ROUND_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		divider_ux1 += rate - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	do_div(divider_ux1, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if (flags & TEGRA_DIVIDER_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		divider_ux1 *= mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	if (divider_ux1 < mul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	divider_ux1 -= mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	if (divider_ux1 > div_mask(width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		return div_mask(width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	return divider_ux1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }