^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/tegra30-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OSC_CTRL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OSC_FREQ_DET 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OSC_FREQ_DET_TRIG BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OSC_FREQ_DET_STATUS 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OSC_FREQ_DET_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OSC_FREQ_DET_CNT_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCLKG_BURST_POLICY 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUPER_CCLKG_DIVIDER 0x36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCLKLP_BURST_POLICY 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUPER_CCLKLP_DIVIDER 0x374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCLK_BURST_POLICY 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUPER_SCLK_DIVIDER 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYSTEM_CLK_RATE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA30_CLK_PERIPH_BANKS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLC_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLC_MISC 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLLM_BASE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLLM_MISC 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLP_BASE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLLP_MISC 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLX_MISC 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLLD_BASE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLLD_MISC 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLLD2_BASE 0x4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLLD2_MISC 0x4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLLE_BASE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLLE_MISC 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLLA_BASE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLA_MISC 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLLU_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLLU_MISC 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLL_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLLDU_MISC_LOCK_ENABLE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PLLE_MISC_LOCK_ENABLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PLL_BASE_LOCK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLLE_MISC_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLLE_AUX 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLLC_OUT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLLM_OUT 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLLP_OUTA 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLLP_OUTB 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PLLA_OUT 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUDIO_SYNC_CLK_I2S0 0x4a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AUDIO_SYNC_CLK_I2S1 0x4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUDIO_SYNC_CLK_I2S2 0x4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUDIO_SYNC_CLK_I2S3 0x4ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUDIO_SYNC_CLK_I2S4 0x4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AUDIO_SYNC_CLK_SPDIF 0x4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_SOURCE_SPDIF_OUT 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_SOURCE_PWM 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_SOURCE_D_AUDIO 0x3d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_SOURCE_DAM0 0x3d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_SOURCE_DAM1 0x3dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_SOURCE_DAM2 0x3e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_SOURCE_3D2 0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_SOURCE_2D 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_SOURCE_HDMI 0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_SOURCE_DSIB 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_SOURCE_SE 0x42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_SOURCE_EMC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AUDIO_SYNC_DOUBLER 0x49c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Tegra CPU clock and reset control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CPU_RESET(cpu) (0x1111ul << (cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_RESET_CCLK_BURST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_RESET_CCLK_DIVIDER 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_RESET_PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_RESET_PLLX_MISC 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_RESET_SOURCE_CSITE 0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_RESET_CCLK_IDLE_POLICY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_RESET_CCLK_RUN_POLICY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* PLLM override registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PMC_PLLM_WB0_OVERRIDE 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct cpu_clk_suspend_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 pllx_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 pllx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 cpu_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 clk_csite_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } tegra30_cpu_clk_sctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static unsigned long input_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static DEFINE_SPINLOCK(cml_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static DEFINE_SPINLOCK(pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) _clk_num, _gate_flags, _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) _clk_num, _gate_flags, _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TEGRA_DIVIDER_ROUND_UP, _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) _gate_flags, _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) _mux_shift, _mux_width, _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) _clk_num, _gate_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 12000000, 1040000000, 520, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 13000000, 1040000000, 480, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 19200000, 1040000000, 325, 6, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 26000000, 1040000000, 520, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 12000000, 832000000, 416, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 13000000, 832000000, 832, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 19200000, 832000000, 260, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 26000000, 832000000, 416, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 12000000, 624000000, 624, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 13000000, 624000000, 624, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 16800000, 600000000, 520, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 19200000, 624000000, 520, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 26000000, 624000000, 624, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 12000000, 600000000, 600, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 13000000, 600000000, 600, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 16800000, 600000000, 500, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 19200000, 600000000, 375, 12, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 26000000, 600000000, 600, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 12000000, 520000000, 520, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 13000000, 520000000, 520, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 19200000, 520000000, 325, 12, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 26000000, 520000000, 520, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 12000000, 416000000, 416, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 13000000, 416000000, 416, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 19200000, 416000000, 260, 12, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 26000000, 416000000, 416, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 12000000, 666000000, 666, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 13000000, 666000000, 666, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 16800000, 666000000, 555, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 19200000, 666000000, 555, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 26000000, 666000000, 666, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 12000000, 600000000, 600, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 13000000, 600000000, 600, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 16800000, 600000000, 500, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 19200000, 600000000, 375, 12, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 26000000, 600000000, 600, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 12000000, 216000000, 432, 12, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 13000000, 216000000, 432, 13, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 16800000, 216000000, 360, 14, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 19200000, 216000000, 360, 16, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 26000000, 216000000, 432, 26, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 9600000, 564480000, 294, 5, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 9600000, 552960000, 288, 5, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 9600000, 24000000, 5, 2, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 28800000, 56448000, 49, 25, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 28800000, 73728000, 64, 25, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 28800000, 24000000, 5, 6, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 12000000, 216000000, 216, 12, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 13000000, 216000000, 216, 13, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 16800000, 216000000, 180, 14, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 19200000, 216000000, 180, 16, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 26000000, 216000000, 216, 26, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 12000000, 594000000, 594, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 13000000, 594000000, 594, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 16800000, 594000000, 495, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 19200000, 594000000, 495, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 26000000, 594000000, 594, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 12000000, 1000000000, 1000, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 13000000, 1000000000, 1000, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 19200000, 1000000000, 625, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 26000000, 1000000000, 1000, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct pdiv_map pllu_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .pdiv = 1, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .pdiv = 2, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 12000000, 480000000, 960, 12, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 13000000, 480000000, 960, 13, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 16800000, 480000000, 400, 7, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 19200000, 480000000, 200, 4, 2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 26000000, 480000000, 960, 26, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* 1.7 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 12000000, 1700000000, 850, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 26000000, 1700000000, 850, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* 1.6 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 12000000, 1600000000, 800, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { 19200000, 1600000000, 500, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 26000000, 1600000000, 800, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* 1.5 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 12000000, 1500000000, 750, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 16800000, 1500000000, 625, 7, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 19200000, 1500000000, 625, 8, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 26000000, 1500000000, 750, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* 1.4 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 12000000, 1400000000, 700, 6, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 16800000, 1400000000, 1000, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 19200000, 1400000000, 875, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 26000000, 1400000000, 700, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* 1.3 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 12000000, 1300000000, 975, 9, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 13000000, 1300000000, 1000, 10, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 26000000, 1300000000, 650, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* 1.2 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 12000000, 1200000000, 1000, 10, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 16800000, 1200000000, 1000, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 19200000, 1200000000, 1000, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 26000000, 1200000000, 600, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* 1.1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 12000000, 1100000000, 825, 9, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 26000000, 1100000000, 550, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 12000000, 1000000000, 1000, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 13000000, 1000000000, 1000, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 19200000, 1000000000, 625, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 26000000, 1000000000, 1000, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct pdiv_map plle_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { .pdiv = 18, .hw_val = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .pdiv = 24, .hw_val = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* PLLE special case: use cpcon field to store cml divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 12000000, 100000000, 150, 1, 18, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 216000000, 100000000, 200, 18, 24, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* PLL parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct tegra_clk_pll_params pll_c_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .base_reg = PLLC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .misc_reg = PLLC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .freq_table = pll_c_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct div_nmp pllm_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .divn_width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .override_divn_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .divm_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .override_divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .override_divp_shift = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct tegra_clk_pll_params pll_m_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .base_reg = PLLM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .misc_reg = PLLM_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .div_nmp = &pllm_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .freq_table = pll_m_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct tegra_clk_pll_params pll_p_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .base_reg = PLLP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .misc_reg = PLLP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .freq_table = pll_p_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .fixed_rate = 408000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct tegra_clk_pll_params pll_a_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .base_reg = PLLA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .misc_reg = PLLA_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .freq_table = pll_a_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct tegra_clk_pll_params pll_d_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .vco_min = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .base_reg = PLLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .misc_reg = PLLD_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static struct tegra_clk_pll_params pll_d2_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .vco_min = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .base_reg = PLLD2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .misc_reg = PLLD2_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct tegra_clk_pll_params pll_u_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .vco_min = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .vco_max = 960000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .base_reg = PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .misc_reg = PLLU_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .pdiv_tohw = pllu_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .freq_table = pll_u_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .vco_max = 1700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .base_reg = PLLX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .misc_reg = PLLX_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .freq_table = pll_x_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .post_rate_change = tegra_cclk_post_pllx_rate_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .input_max = 216000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .cf_max = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .vco_min = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .vco_max = 2400000000U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .base_reg = PLLE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .misc_reg = PLLE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .lock_mask = PLLE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .pdiv_tohw = plle_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .freq_table = pll_e_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .fixed_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static unsigned long tegra30_input_freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [ 0] = 13000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [ 1] = 16800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [ 4] = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [ 5] = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [ 8] = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [ 9] = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [12] = 26000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct tegra_devclk devclks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static void __init tegra30_pll_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* PLLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) &pll_c_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) clks[TEGRA30_CLK_PLL_C] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* PLLC_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* PLLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) CLK_SET_RATE_GATE, &pll_m_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clks[TEGRA30_CLK_PLL_M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* PLLM_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) clk_base + PLLM_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* PLLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) &pll_x_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) clks[TEGRA30_CLK_PLL_X] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* PLLX_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* PLLU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &pll_u_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) clks[TEGRA30_CLK_PLL_U] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* PLLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) &pll_d_params, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) clks[TEGRA30_CLK_PLL_D] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* PLLD_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* PLLD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &pll_d2_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) clks[TEGRA30_CLK_PLL_D2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* PLLD2_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* PLLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ARRAY_SIZE(pll_e_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) clk_base + PLLE_AUX, 2, 1, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) clks[TEGRA30_CLK_PLL_E] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "pll_p_cclkg", "pll_p_out4_cclkg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "pll_p_out3_cclkg", "unused", "pll_x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "pll_p_cclklp", "pll_p_out4_cclklp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "pll_p_out3_cclklp", "unused", "pll_x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "pll_x_out0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "pll_p_out3", "pll_p_out2", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "clk_32k", "pll_m_out1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static void __init tegra30_super_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Clock input to cclk_g divided from pll_p using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * U71 divider of cclk_g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) clk_base + SUPER_CCLKG_DIVIDER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) clk_register_clkdev(clk, "pll_p_cclkg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Clock input to cclk_g divided from pll_p_out3 using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * U71 divider of cclk_g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) clk_base + SUPER_CCLKG_DIVIDER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Clock input to cclk_g divided from pll_p_out4 using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * U71 divider of cclk_g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clk_base + SUPER_CCLKG_DIVIDER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* CCLKG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ARRAY_SIZE(cclk_g_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) clk_base + CCLKG_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) clks[TEGRA30_CLK_CCLK_G] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Clock input to cclk_lp divided from pll_p using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * U71 divider of cclk_lp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) clk_base + SUPER_CCLKLP_DIVIDER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) clk_register_clkdev(clk, "pll_p_cclklp", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * Clock input to cclk_lp divided from pll_p_out3 using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * U71 divider of cclk_lp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) clk_base + SUPER_CCLKLP_DIVIDER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * Clock input to cclk_lp divided from pll_p_out4 using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * U71 divider of cclk_lp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) clk_base + SUPER_CCLKLP_DIVIDER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* CCLKLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ARRAY_SIZE(cclk_lp_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) clk_base + CCLKLP_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) TEGRA_DIVIDER_2, 4, 8, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) clks[TEGRA30_CLK_CCLK_LP] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) clk = tegra_clk_register_super_mux("sclk", sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ARRAY_SIZE(sclk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) clk_base + SCLK_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) 0, 4, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) clks[TEGRA30_CLK_SCLK] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* twd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) clks[TEGRA30_CLK_TWD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "pll_a_out0", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) "pll_d2_out0", "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "pll_d2_out0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static struct tegra_periph_init_data tegra_periph_clk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static void __init tegra30_periph_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct tegra_periph_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* dsia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) 0, 48, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) clks[TEGRA30_CLK_DSIA] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* pcie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 70, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) clks[TEGRA30_CLK_PCIE] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* afi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) clks[TEGRA30_CLK_AFI] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* emc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) clks[TEGRA30_CLK_EMC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clks[TEGRA30_CLK_MC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* cml0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) 0, 0, &cml_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) clks[TEGRA30_CLK_CML0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* cml1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) 1, 0, &cml_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) clks[TEGRA30_CLK_CML1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) data = &tegra_periph_clk_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) clk = tegra_clk_register_periph_data(clk_base, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) clks[data->clk_id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) data = &tegra_periph_nodiv_clk_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clk = tegra_clk_register_periph_nodiv(data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) data->p.parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) data->num_parents, &data->periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) clk_base, data->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) clks[data->clk_id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Tegra30 CPU clock and reset control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void tegra30_wait_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) reg = readl(clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void tegra30_put_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) writel(CPU_RESET(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static void tegra30_cpu_out_of_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) writel(CPU_RESET(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static void tegra30_enable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) writel(CPU_CLOCK(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) reg = readl(clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static void tegra30_disable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) writel(reg | CPU_CLOCK(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static bool tegra30_cpu_rail_off_ready(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unsigned int cpu_rst_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int cpu_pwr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) cpu_rst_status = readl(clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tegra_pmc_cpu_is_powered(2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) tegra_pmc_cpu_is_powered(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static void tegra30_cpu_clock_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* switch coresite to clk_m, save off original source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) tegra30_cpu_clk_sctx.clk_csite_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) readl(clk_base + CLK_RESET_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) tegra30_cpu_clk_sctx.cpu_burst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) readl(clk_base + CLK_RESET_CCLK_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) tegra30_cpu_clk_sctx.pllx_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) readl(clk_base + CLK_RESET_PLLX_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) tegra30_cpu_clk_sctx.pllx_misc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) readl(clk_base + CLK_RESET_PLLX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) tegra30_cpu_clk_sctx.cclk_divider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) readl(clk_base + CLK_RESET_CCLK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static void tegra30_cpu_clock_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) unsigned int reg, policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) u32 misc, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Is CPU complex already running on PLLX? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) reg = readl(clk_base + CLK_RESET_CCLK_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (policy == CLK_RESET_CCLK_IDLE_POLICY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) else if (policy == CLK_RESET_CCLK_RUN_POLICY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (misc != tegra30_cpu_clk_sctx.pllx_misc ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) base != tegra30_cpu_clk_sctx.pllx_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* restore PLLX settings if CPU is on different PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) writel(tegra30_cpu_clk_sctx.pllx_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) clk_base + CLK_RESET_PLLX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) writel(tegra30_cpu_clk_sctx.pllx_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) clk_base + CLK_RESET_PLLX_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* wait for PLL stabilization if PLLX was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * Restore original burst policy setting for calls resulting from CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * LP2 in idle or system suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) writel(tegra30_cpu_clk_sctx.cclk_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) clk_base + CLK_RESET_CCLK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) writel(tegra30_cpu_clk_sctx.cpu_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) clk_base + CLK_RESET_CCLK_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) writel(tegra30_cpu_clk_sctx.clk_csite_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) clk_base + CLK_RESET_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .wait_for_reset = tegra30_wait_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .put_in_reset = tegra30_put_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .out_of_reset = tegra30_cpu_out_of_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .enable_clock = tegra30_enable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .disable_clock = tegra30_disable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .rail_off_ready = tegra30_cpu_rail_off_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .suspend = tegra30_cpu_clock_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .resume = tegra30_cpu_clock_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct tegra_clk_init_table init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static void __init tegra30_clock_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * Some clocks may be used by different drivers depending on the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * configuration. List those here to register them twice in the clock lookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * table under two names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const struct of_device_id pmc_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) { .compatible = "nvidia,tegra30-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static struct tegra_audio_clk_info tegra30_audio_plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) clk = of_clk_src_onecell_get(clkspec, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (clkspec->args[0] == TEGRA30_CLK_EMC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!tegra20_clk_emc_driver_available(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static void __init tegra30_clock_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) pr_err("ioremap tegra30 CAR failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) node = of_find_matching_node(NULL, pmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pr_err("Failed to find pmc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pmc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (!pmc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) pr_err("Can't map pmc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) TEGRA30_CLK_PERIPH_BANKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) NULL) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) tegra_fixed_clk_init(tegra30_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) tegra30_pll_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) tegra30_super_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) tegra30_periph_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) tegra30_audio_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ARRAY_SIZE(tegra30_audio_plls), 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) tegra_cpu_car_ops = &tegra30_cpu_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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