^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/tegra210-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/reset/tegra210-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * banks present in the Tegra210 CAR IP block. The banks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * periph_regs[] in drivers/clk/tegra/clk.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA210_CAR_BANK_COUNT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_SOURCE_CSITE 0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_SOURCE_EMC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_SOURCE_SOR1 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_SOURCE_SOR0 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_SOURCE_LA 0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_SOURCE_SDMMC2 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_SOURCE_SDMMC4 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_SOURCE_EMC_DLL 0x664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLLC_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLLC_OUT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLLC_MISC0 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLLC_MISC1 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLLC_MISC2 0x5d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLLC_MISC3 0x5d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLLC2_BASE 0x4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLLC2_MISC0 0x4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLLC2_MISC1 0x4f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLLC2_MISC2 0x4f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLLC2_MISC3 0x4f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLC3_BASE 0x4fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLC3_MISC0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLLC3_MISC1 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLLC3_MISC2 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLC3_MISC3 0x50c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLLM_BASE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLM_MISC1 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLLM_MISC2 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLLP_BASE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLLP_MISC0 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLLP_MISC1 0x680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLLA_BASE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLLA_MISC0 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLLA_MISC1 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLA_MISC2 0x5d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLLD_BASE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLLD_MISC0 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLLD_MISC1 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLLU_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLLU_OUTA 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PLLU_MISC0 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PLLU_MISC1 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLLX_MISC0 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PLLX_MISC1 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLLX_MISC2 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLLX_MISC3 0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLLX_MISC4 0x5f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLLX_MISC5 0x5f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLLE_BASE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PLLE_MISC0 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PLLD2_BASE 0x4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PLLD2_MISC0 0x4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PLLD2_MISC1 0x570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLLD2_MISC2 0x574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PLLD2_MISC3 0x578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PLLE_AUX 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLLRE_BASE 0x4c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PLLRE_MISC0 0x4c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PLLRE_OUT1 0x4cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PLLDP_BASE 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PLLDP_MISC 0x594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLLC4_BASE 0x5a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLLC4_MISC0 0x5a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLLC4_OUT 0x5e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PLLMB_BASE 0x5e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLLMB_MISC1 0x5ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PLLA1_BASE 0x6a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PLLA1_MISC0 0x6a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PLLA1_MISC1 0x6ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PLLA1_MISC2 0x6b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PLLA1_MISC3 0x6b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PLLU_IDDQ_BIT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PLLCX_IDDQ_BIT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PLLRE_IDDQ_BIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PLLA_IDDQ_BIT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PLLD_IDDQ_BIT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PLLSS_IDDQ_BIT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PLLM_IDDQ_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PLLMB_IDDQ_BIT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PLLXP_IDDQ_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PLLCX_RESET_BIT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PLL_BASE_LOCK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PLLCX_BASE_LOCK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PLLE_MISC_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PLLRE_MISC_LOCK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PLL_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PLLC_MISC_LOCK_ENABLE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PLLDU_MISC_LOCK_ENABLE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PLLU_MISC_LOCK_ENABLE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PLLE_MISC_LOCK_ENABLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PLLRE_MISC_LOCK_ENABLE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PLLSS_MISC_LOCK_ENABLE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PLLP_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PLLM_MISC_LOCK_ENABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PLLMB_MISC_LOCK_ENABLE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PLLA_MISC_LOCK_ENABLE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PLLU_MISC_LOCK_ENABLE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PLLD_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PLLA_SDM_DIN_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PLLA_SDM_EN_MASK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PLLD_SDM_EN_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PLLD2_SDM_EN_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PLLD2_SSC_EN_MASK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PLLDP_SS_CFG 0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PLLDP_SDM_EN_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PLLDP_SSC_EN_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PLLDP_SS_CTRL1 0x59c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PLLDP_SS_CTRL2 0x5a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PMC_PLLM_WB0_OVERRIDE 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define UTMIP_PLL_CFG2 0x488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define UTMIP_PLL_CFG1 0x484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SATA_PLL_CFG0 0x490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define XUSBIO_PLL_CFG0 0x51c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define UTMIPLL_HW_PWRDN_CFG0 0x52c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PLLU_HW_PWRDN_CFG0 0x530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define XUSB_PLL_CFG0 0x534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SPARE_REG0 0x55c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_M_DIVISOR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_M_DIVISOR_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_MASK_ARM 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MISC_CLK_ENB 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RST_DFLL_DVCO 0x2f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DVFS_DFLL_RESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CPU_SOFTRST_CTRL 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define LVL2_CLK_GATE_OVRA 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define LVL2_CLK_GATE_OVRC 0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define LVL2_CLK_GATE_OVRD 0x3a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define LVL2_CLK_GATE_OVRE 0x554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* I2S registers to handle during APE MBIST WAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA210_I2S_BASE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA210_I2S_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA210_I2S_CTRLS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA210_I2S_CG 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA210_I2S_CTRL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* DISPA registers to handle during MBIST WAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DC_CMD_DISPLAY_COMMAND 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DC_COM_DSC_TOP_CTL 0xcf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* VIC register to handle during MBIST WAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* APE, DISPA and VIC base addesses needed for MBIST WAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA210_AHUB_BASE 0x702d0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA210_DISPA_BASE 0x54200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA210_VIC_BASE 0x54340000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * SDM fractional divisor is 16-bit 2's complement signed number within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * indicate that SDM is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PLL_SDM_COEFF BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* This macro returns ndiv effective scaled to SDM range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Tegra CPU clock and reset control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct cpu_clk_suspend_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 clk_csite_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } tegra210_cpu_clk_sctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct tegra210_domain_mbist_war {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) const u32 lvl2_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const u32 lvl2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const unsigned int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const unsigned int *clk_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void __iomem *ahub_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void __iomem *dispa_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void __iomem *vic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static unsigned long osc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static unsigned long pll_ref_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static DEFINE_SPINLOCK(pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static DEFINE_SPINLOCK(pll_e_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static DEFINE_SPINLOCK(pll_re_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static DEFINE_SPINLOCK(pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static DEFINE_SPINLOCK(sor0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static DEFINE_SPINLOCK(sor1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static DEFINE_SPINLOCK(emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static DEFINE_MUTEX(lvl2_ovr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* possible OSC frequencies in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static unsigned long tegra210_input_freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [5] = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [8] = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PLL_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PLLCX_MISC1_IDDQ (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PLLCX_MISC0_RESET (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PLLCX_MISC1_WRITE_MASK 0x08003cff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PLLCX_MISC2_WRITE_MASK 0xffffff17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* PLLA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PLLA_BASE_IDDQ (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PLLA_BASE_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PLLA_MISC2_EN_SDM (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PLLA_MISC0_WRITE_MASK 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PLLA_MISC2_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PLLA_MISC2_WRITE_MASK 0x06ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* PLLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PLLD_MISC0_EN_SDM (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PLLD_MISC0_IDDQ (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PLLD_MISC1_DEFAULT_VALUE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PLLD_MISC1_WRITE_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* PLLD2 and PLLDP and PLLC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PLLDSS_BASE_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PLLDSS_BASE_IDDQ (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PLLDSS_BASE_REF_SEL_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* PLLRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PLLRE_MISC0_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PLLRE_MISC0_IDDQ (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PLLRE_BASE_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* PLLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PLLX_USE_DYN_RAMP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PLLX_BASE_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PLLX_MISC2_NDIV_NEW_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PLLX_MISC3_IDDQ (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PLLX_MISC0_WRITE_MASK 0x10c40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PLLX_MISC1_DEFAULT_VALUE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PLLX_MISC1_WRITE_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PLLX_MISC2_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PLLX_MISC2_WRITE_MASK 0xffffff11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PLLX_MISC4_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PLLX_MISC4_WRITE_MASK 0x8000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PLLX_MISC5_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PLLX_MISC5_WRITE_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PLLX_HW_CTRL_CFG 0x548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* PLLMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PLLMB_BASE_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PLLMB_MISC1_IDDQ (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* PLLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PLLP_BASE_OVERRIDE (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PLLP_BASE_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PLLP_MISC0_IDDQ (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define PLLP_MISC1_HSIO_EN_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PLLP_MISC1_XUSB_EN_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PLLP_MISC1_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PLLP_MISC0_WRITE_MASK 0xdc6000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PLLP_MISC1_WRITE_MASK 0x70ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* PLLU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PLLU_BASE_LOCK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define PLLU_BASE_OVERRIDE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define PLLU_BASE_CLKENABLE_USB (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define PLLU_BASE_CLKENABLE_48M (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PLLU_BASE_CLKENABLE_HSIC |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PLLU_BASE_CLKENABLE_ICUSB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PLLU_BASE_CLKENABLE_48M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PLLU_MISC0_IDDQ (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PLLU_MISC1_DEFAULT_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define PLLU_MISC0_WRITE_MASK 0xbfffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define PLLU_MISC1_WRITE_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void tegra210_xusb_pll_hw_control_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) void tegra210_xusb_pll_hw_sequence_start(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void tegra210_sata_pll_hw_control_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) val = readl_relaxed(clk_base + SATA_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) writel_relaxed(val, clk_base + SATA_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void tegra210_sata_pll_hw_sequence_start(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = readl_relaxed(clk_base + SATA_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val |= SATA_PLL_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) writel_relaxed(val, clk_base + SATA_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) void tegra210_set_sata_pll_seq_sw(bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) val = readl_relaxed(clk_base + SATA_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel_relaxed(val, clk_base + SATA_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) void tegra210_clk_emc_dll_enable(bool flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void tegra210_clk_emc_update_setting(u32 emc_src_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val = readl_relaxed(clk_base + mbist->lvl2_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writel_relaxed(val, clk_base + mbist->lvl2_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 csi_src, ovra, ovre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) spin_lock_irqsave(&pll_d_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) csi_src = readl_relaxed(clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) writel_relaxed(csi_src, clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) spin_unlock_irqrestore(&pll_d_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 ovra, dsc_top_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 ovre, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) void __iomem *i2s_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 ovrc, ovre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel_relaxed(ovre | BIT(10) | BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) i2s_base = ahub_base + TEGRA210_I2S_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 i2s_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel_relaxed(i2s_ctrl | BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) i2s_base + TEGRA210_I2S_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) readl(i2s_base + TEGRA210_I2S_CG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) readl(i2s_base + TEGRA210_I2S_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) i2s_base += TEGRA210_I2S_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static inline void _pll_misc_chk_default(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct tegra_clk_pll_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u8 misc_num, u32 default_val, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) boot_val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) default_val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (boot_val != default_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) pr_warn("boot misc%d 0x%x: expected 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) misc_num, boot_val, default_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pr_warn(" (comparison mask = 0x%x)\n", mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) params->defaults_set = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * that changes NDIV only, while PLL is already locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 default_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) _pll_misc_chk_default(clk_base, params, 0, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PLLCX_MISC0_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) _pll_misc_chk_default(clk_base, params, 1, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PLLCX_MISC1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) default_val = PLLCX_MISC2_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) _pll_misc_chk_default(clk_base, params, 2, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PLLCX_MISC2_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) default_val = PLLCX_MISC3_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) _pll_misc_chk_default(clk_base, params, 3, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PLLCX_MISC3_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void tegra210_pllcx_set_defaults(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct tegra_clk_pll *pllcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pllcx->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* PLL is ON: only check if defaults already set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pllcx_check_defaults(pllcx->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!pllcx->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pr_warn("%s already enabled. Postponing set full defaults\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Defaults assert PLL reset, and set IDDQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clk_base + pllcx->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) clk_base + pllcx->params->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) clk_base + pllcx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clk_base + pllcx->params->ext_misc_reg[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tegra210_pllcx_set_defaults("PLL_C", pllcx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tegra210_pllcx_set_defaults("PLL_C2", pllcx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tegra210_pllcx_set_defaults("PLL_C3", pllcx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tegra210_pllcx_set_defaults("PLL_A1", pllcx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * PLLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Fractional SDM is allowed to provide exact audio rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 val = readl_relaxed(clk_base + plla->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) plla->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (val & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (val & PLLA_BASE_IDDQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pr_warn("PLL_A boot enabled with IDDQ set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) plla->params->defaults_set = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pr_warn("PLL_A already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) _pll_misc_chk_default(clk_base, plla->params, 0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ~mask & PLLA_MISC0_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) _pll_misc_chk_default(clk_base, plla->params, 2, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PLLA_MISC2_EN_DYNRAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) val |= PLLA_MISC0_DEFAULT_VALUE & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val |= PLLA_BASE_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) writel_relaxed(val, clk_base + plla->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) clk_base + plla->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) clk_base + plla->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * PLLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * PLL with fractional SDM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u32 mask = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) plld->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (readl_relaxed(clk_base + plld->params->base_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) val = PLLD_MISC1_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) _pll_misc_chk_default(clk_base, plld->params, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) val, PLLD_MISC1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) _pll_misc_chk_default(clk_base, plld->params, 0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ~mask & PLLD_MISC0_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!plld->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pr_warn("PLL_D already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) val |= PLLD_MISC0_DEFAULT_VALUE & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) val &= PLLD_MISC0_DSI_CLKENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val |= PLLD_MISC0_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* set IDDQ, enable lock detect, disable SDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) plld->params->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * PLLD2, PLLDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 default_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) plldss->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (val & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (val & PLLDSS_BASE_IDDQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pr_warn("plldss boot enabled with IDDQ set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) plldss->params->defaults_set = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* ignore lock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default_val = misc0_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PLLDSS_MISC0_WRITE_MASK &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) (~PLLDSS_MISC0_LOCK_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * If SSC is used, check all settings, otherwise just confirm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * that SSC is not used on boot as well. Do nothing when using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * this function for PLLC4 that has only MISC0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (plldss->params->ssc_ctrl_en_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) default_val = misc1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) _pll_misc_chk_default(clk_base, plldss->params, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) default_val = misc2_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) _pll_misc_chk_default(clk_base, plldss->params, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) default_val = misc3_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) _pll_misc_chk_default(clk_base, plldss->params, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) } else if (plldss->params->ext_misc_reg[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) default_val = misc1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) _pll_misc_chk_default(clk_base, plldss->params, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) (~PLLDSS_MISC1_CFG_EN_SDM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!plldss->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pr_warn("%s already enabled. Postponing set full defaults\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) pll_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) writel_relaxed(val, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) plldss->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) val &= ~PLLDSS_MISC0_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* set IDDQ, enable lock detect, configure SDM/SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) val |= PLLDSS_BASE_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) writel_relaxed(val, clk_base + plldss->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* When using this function for PLLC4 exit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!plldss->params->ext_misc_reg[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) writel_relaxed(misc0_val, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) plldss->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) writel_relaxed(misc0_val, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) plldss->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* if SSC used set by 1st enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) clk_base + plldss->params->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PLLD2_MISC1_CFG_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PLLDP_MISC1_CFG_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * PLLC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * PLLRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * VCO is exposed to the clock tree directly along with post-divider output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pllre->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (val & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) val &= PLLRE_BASE_DEFAULT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (val != PLLRE_BASE_DEFAULT_VALUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pr_warn("pllre boot base 0x%x : expected 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) val, PLLRE_BASE_DEFAULT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pr_warn("(comparison mask = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PLLRE_BASE_DEFAULT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) pllre->params->defaults_set = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Ignore lock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) _pll_misc_chk_default(clk_base, pllre->params, 0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ~mask & PLLRE_MISC0_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* The PLL doesn't work if it's in IDDQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (val & PLLRE_MISC0_IDDQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pr_warn("unexpected IDDQ bit set for enabled clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!pllre->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* set IDDQ, enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) val &= ~PLLRE_BASE_DEFAULT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) writel_relaxed(val, clk_base + pllre->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) clk_base + pllre->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned long input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* cf rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!IS_ERR_OR_NULL(hw->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) input_rate = 38400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) switch (input_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case 12800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) *step_a = 0x2B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) *step_b = 0x0B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) *step_a = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) *step_b = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case 38400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) *step_a = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) *step_b = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pr_err("%s: Unexpected reference rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) __func__, input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static void pllx_check_defaults(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u32 default_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) default_val = PLLX_MISC0_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* ignore lock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) default_val = PLLX_MISC1_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PLLX_MISC1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* ignore all but control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) default_val = PLLX_MISC2_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) _pll_misc_chk_default(clk_base, pll->params, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) default_val, PLLX_MISC2_EN_DYNRAMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PLLX_MISC3_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) default_val = PLLX_MISC4_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PLLX_MISC4_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) default_val = PLLX_MISC5_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PLLX_MISC5_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u32 step_a, step_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) pllx->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Get ready dyn ramp state machine settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pllx_check_defaults(pllx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!pllx->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pr_warn("PLL_X already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Configure dyn ramp, disable lock override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) val &= ~PLLX_MISC0_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Enable lock detect and CPU output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pllx->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) pllx->params->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* Configure dyn ramp state machine, disable lock override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Set IDDQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pllx->params->ext_misc_reg[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* Disable SDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) pllx->params->ext_misc_reg[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pllx->params->ext_misc_reg[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* PLLMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) pllmb->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (val & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ~mask & PLLMB_MISC1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!pllmb->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* set IDDQ, enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) clk_base + pllmb->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * PLLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * VCO is exposed to the clock tree directly along with post-divider output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mask |= PLLP_MISC0_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) _pll_misc_chk_default(clk_base, pll->params, 0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ~mask & PLLP_MISC0_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Ignore branch controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) val = PLLP_MISC1_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) _pll_misc_chk_default(clk_base, pll->params, 1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ~mask & PLLP_MISC1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) pllp->params->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (val & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) pllp_check_defaults(pllp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!pllp->params->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pr_warn("PLL_P already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) val |= PLLP_MISC0_DEFAULT_VALUE & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* set IDDQ, enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) clk_base + pllp->params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* Preserve branch control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * PLLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * VCO is exposed to the clock tree directly along with post-divider output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static void pllu_check_defaults(struct tegra_clk_pll_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) bool hw_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* Ignore lock enable (will be set) and IDDQ if under h/w control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) _pll_misc_chk_default(clk_base, params, 0, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ~mask & PLLU_MISC0_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) val = PLLU_MISC1_DEFAULT_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) mask = PLLU_MISC1_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) _pll_misc_chk_default(clk_base, params, 1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ~mask & PLLU_MISC1_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 val = readl_relaxed(clk_base + pllu->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pllu->defaults_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (val & PLL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * PLL is ON: check if defaults already set, then set those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * that can be updated in flight.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) pllu_check_defaults(pllu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!pllu->defaults_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pr_warn("PLL_U already enabled. Postponing set full defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* Enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) val &= ~PLLU_MISC0_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) val &= ~PLLU_MISC1_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* set IDDQ, enable lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) clk_base + pllu->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) clk_base + pllu->ext_misc_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define mask(w) ((1 << (w)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define divm_mask(p) mask(p->params->div_nmp->divm_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define divn_mask(p) mask(p->params->div_nmp->divn_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) mask(p->params->div_nmp->divp_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) u32 reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) udelay(PLL_LOCKDET_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) val = readl_relaxed(clk_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if ((val & mask) == mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) udelay(PLL_LOCKDET_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct tegra_clk_pll_freq_table *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) u32 val, base, ndiv_new_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) << PLLX_MISC2_NDIV_NEW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) val &= (~ndiv_new_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) val |= PLLX_MISC2_EN_DYNRAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PLLX_MISC2_DYNRAMP_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) base = readl_relaxed(clk_base + pllx->params->base_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) (~divn_mask_shifted(pllx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) base |= cfg->n << pllx->params->div_nmp->divn_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) writel_relaxed(base, clk_base + pllx->params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) val &= ~PLLX_MISC2_EN_DYNRAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) cfg->input_rate / cfg->m * cfg->n /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * Common configuration for PLLs with fixed input divider policy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * - always set fixed M-value based on the reference rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * - always set P-value value 1:1 for output rates above VCO minimum, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * choose minimum necessary P-value for output rates below VCO maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * - calculate N-value based on selected M and P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * - calculate SDM_DIN fractional part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) unsigned long rate, unsigned long input_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct tegra_clk_pll_params *params = pll->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) unsigned long cf, p_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) u32 pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) p = DIV_ROUND_UP(params->vco_min, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) p = params->round_p_to_pdiv(p, &pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) p = rate >= params->vco_min ? 1 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (p < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) cfg->p = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Store P as HW value, as that is what is expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) p_rate = rate * p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (p_rate > params->vco_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) p_rate = params->vco_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) cf = input_rate / cfg->m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) cfg->n = p_rate / cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) cfg->sdm_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) cfg->output_rate = input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (params->sdm_ctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) unsigned long rem = p_rate - cf * cfg->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* If ssc is enabled SDM enabled as well, even for integer n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (rem || params->ssc_ctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) u64 s = rem * PLL_SDM_COEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) do_div(s, cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) s -= PLL_SDM_COEFF / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) cfg->sdm_data = sdin_din_to_data(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) cfg->output_rate *= sdin_get_n_eff(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) cfg->output_rate *= cfg->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) cfg->output_rate /= p * cfg->m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) cfg->input_rate = input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * @cfg: struct tegra_clk_pll_freq_table * cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * For Normal mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * Fvco = Fref * NDIV / MDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * For fractional mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) cfg->n = sdin_get_n_eff(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) cfg->m *= PLL_SDM_COEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) unsigned long vco_min = params->vco_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) vco_min = min(vco_min, params->vco_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return vco_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static struct div_nmp pllx_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * PLL post divider maps - two types: quasi-linear and exponential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * post divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define PLL_QLIN_PDIV_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) { .pdiv = 9, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) { .pdiv = 10, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { .pdiv = 12, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { .pdiv = 15, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) { .pdiv = 18, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) { .pdiv = 20, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) { .pdiv = 24, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) { .pdiv = 30, .hw_val = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) { .pdiv = 32, .hw_val = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) *pdiv = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return pll_qlin_pdiv_to_hw[i].pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define PLL_EXPO_PDIV_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) { .pdiv = 4, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) { .pdiv = 8, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) { .pdiv = 16, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) { .pdiv = 32, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) { .pdiv = 64, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) { .pdiv = 128, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) u32 i = fls(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (i == ffs(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (i <= PLL_EXPO_PDIV_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) *pdiv = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static struct tegra_clk_pll_params pll_x_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .cf_max = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .vco_min = 1350000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .vco_max = 3000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .base_reg = PLLX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .misc_reg = PLLX_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .ext_misc_reg[0] = PLLX_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .ext_misc_reg[1] = PLLX_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .ext_misc_reg[2] = PLLX_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .ext_misc_reg[3] = PLLX_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .ext_misc_reg[4] = PLLX_MISC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .ext_misc_reg[5] = PLLX_MISC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .iddq_reg = PLLX_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .iddq_bit_idx = PLLXP_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .mdiv_default = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .dyn_ramp_reg = PLLX_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .stepa_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .stepb_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .div_nmp = &pllx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .freq_table = pll_x_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .dyn_ramp = tegra210_pllx_dyn_ramp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .set_defaults = tegra210_pllx_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static struct div_nmp pllc_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .divn_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) { 12000000, 510000000, 85, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static struct tegra_clk_pll_params pll_c_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .input_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .cf_max = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .base_reg = PLLC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .misc_reg = PLLC_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .iddq_reg = PLLC_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .iddq_bit_idx = PLLCX_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .reset_reg = PLLC_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .reset_bit_idx = PLLCX_RESET_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .ext_misc_reg[0] = PLLC_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .ext_misc_reg[1] = PLLC_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .ext_misc_reg[2] = PLLC_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .ext_misc_reg[3] = PLLC_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .mdiv_default = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .div_nmp = &pllc_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .set_defaults = _pllc_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static struct div_nmp pllcx_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .divn_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static struct tegra_clk_pll_params pll_c2_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .input_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .cf_max = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .base_reg = PLLC2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .misc_reg = PLLC2_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .iddq_reg = PLLC2_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .iddq_bit_idx = PLLCX_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .reset_reg = PLLC2_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .reset_bit_idx = PLLCX_RESET_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .lock_mask = PLLCX_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .mdiv_default = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .div_nmp = &pllcx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .ext_misc_reg[0] = PLLC2_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .ext_misc_reg[1] = PLLC2_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .ext_misc_reg[2] = PLLC2_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .ext_misc_reg[3] = PLLC2_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .set_defaults = _pllc2_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static struct tegra_clk_pll_params pll_c3_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .input_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .cf_max = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .base_reg = PLLC3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .misc_reg = PLLC3_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .lock_mask = PLLCX_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .iddq_reg = PLLC3_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .iddq_bit_idx = PLLCX_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .reset_reg = PLLC3_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .reset_bit_idx = PLLCX_RESET_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .mdiv_default = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .div_nmp = &pllcx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .ext_misc_reg[0] = PLLC3_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .ext_misc_reg[1] = PLLC3_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .ext_misc_reg[2] = PLLC3_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .ext_misc_reg[3] = PLLC3_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .set_defaults = _pllc3_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static struct div_nmp pllss_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .divp_shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) { 12000000, 600000000, 50, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static const struct clk_div_table pll_vco_post_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) { .val = 4, .div = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) { .val = 5, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) { .val = 6, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) { .val = 7, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) { .val = 8, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) { .val = 9, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) { .val = 10, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) { .val = 11, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) { .val = 12, .div = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) { .val = 13, .div = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) { .val = 14, .div = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) { .val = 0, .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static struct tegra_clk_pll_params pll_c4_vco_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .input_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .cf_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .vco_min = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .vco_max = 1080000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .base_reg = PLLC4_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .misc_reg = PLLC4_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .ext_misc_reg[0] = PLLC4_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .iddq_reg = PLLC4_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .iddq_bit_idx = PLLSS_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .mdiv_default = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .div_nmp = &pllss_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .freq_table = pll_c4_vco_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .set_defaults = tegra210_pllc4_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) { 38400000, 297600000, 93, 4, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) { 38400000, 400000000, 125, 4, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) { 38400000, 532800000, 111, 4, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) { 38400000, 665600000, 104, 3, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) { 38400000, 800000000, 125, 3, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) { 38400000, 931200000, 97, 4, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) { 38400000, 1065600000, 111, 4, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) { 38400000, 1200000000, 125, 4, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) { 38400000, 1331200000, 104, 3, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) { 38400000, 1459200000, 76, 2, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) { 38400000, 1600000000, 125, 3, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static struct div_nmp pllm_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .override_divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .override_divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .override_divp_shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static struct tegra_clk_pll_params pll_m_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .input_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .input_max = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .cf_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .vco_min = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .vco_max = 1866000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .base_reg = PLLM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .misc_reg = PLLM_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .iddq_reg = PLLM_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .iddq_bit_idx = PLLM_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .ext_misc_reg[0] = PLLM_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .ext_misc_reg[1] = PLLM_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .div_nmp = &pllm_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .freq_table = pll_m_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static struct tegra_clk_pll_params pll_mb_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .input_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .input_max = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .cf_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .vco_min = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .vco_max = 1866000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .base_reg = PLLMB_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .misc_reg = PLLMB_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .iddq_reg = PLLMB_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .iddq_bit_idx = PLLMB_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .ext_misc_reg[0] = PLLMB_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .div_nmp = &pllm_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .freq_table = pll_m_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .set_defaults = tegra210_pllmb_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* PLLE special case: use cpcon field to store cml divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) { 672000000, 100000000, 125, 42, 0, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) { 624000000, 100000000, 125, 39, 0, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) { 336000000, 100000000, 125, 21, 0, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) { 312000000, 100000000, 200, 26, 0, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) { 38400000, 100000000, 125, 2, 0, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) { 12000000, 100000000, 200, 1, 0, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static struct div_nmp plle_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .divp_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static struct tegra_clk_pll_params pll_e_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .cf_max = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .vco_min = 1600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .vco_max = 2500000000U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .base_reg = PLLE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .misc_reg = PLLE_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .aux_reg = PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .lock_mask = PLLE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .div_nmp = &plle_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .freq_table = pll_e_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .fixed_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) { 12000000, 672000000, 56, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) { 38400000, 672000000, 70, 4, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static struct div_nmp pllre_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .divp_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static struct tegra_clk_pll_params pll_re_vco_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .input_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .cf_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .vco_min = 350000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .base_reg = PLLRE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .misc_reg = PLLRE_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .lock_mask = PLLRE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .ext_misc_reg[0] = PLLRE_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .iddq_reg = PLLRE_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .iddq_bit_idx = PLLRE_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .div_nmp = &pllre_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .freq_table = pll_re_vco_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .set_defaults = tegra210_pllre_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static struct div_nmp pllp_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .divn_shift = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) { 12000000, 408000000, 34, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static struct tegra_clk_pll_params pll_p_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .input_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .cf_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .vco_min = 350000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .base_reg = PLLP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .misc_reg = PLLP_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .iddq_reg = PLLP_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .iddq_bit_idx = PLLXP_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .ext_misc_reg[0] = PLLP_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .ext_misc_reg[1] = PLLP_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .freq_table = pll_p_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .fixed_rate = 408000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .set_defaults = tegra210_pllp_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static struct tegra_clk_pll_params pll_a1_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .input_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .cf_max = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .base_reg = PLLA1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .misc_reg = PLLA1_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .lock_mask = PLLCX_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .iddq_reg = PLLA1_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .iddq_bit_idx = PLLCX_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .reset_reg = PLLA1_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .reset_bit_idx = PLLCX_RESET_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .div_nmp = &pllc_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .ext_misc_reg[0] = PLLA1_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .ext_misc_reg[1] = PLLA1_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .ext_misc_reg[2] = PLLA1_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .ext_misc_reg[3] = PLLA1_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .set_defaults = _plla1_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static struct div_nmp plla_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) { 12000000, 240000000, 60, 1, 3, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) { 38400000, 240000000, 75, 3, 3, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) { 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static struct tegra_clk_pll_params pll_a_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .vco_min = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .base_reg = PLLA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .misc_reg = PLLA_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .iddq_reg = PLLA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .iddq_bit_idx = PLLA_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .div_nmp = &plla_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .sdm_din_reg = PLLA_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .sdm_din_mask = PLLA_SDM_DIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .sdm_ctrl_reg = PLLA_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .ext_misc_reg[0] = PLLA_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .ext_misc_reg[1] = PLLA_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .ext_misc_reg[2] = PLLA_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .freq_table = pll_a_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .set_defaults = tegra210_plla_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .set_gain = tegra210_clk_pll_set_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .adjust_vco = tegra210_clk_adjust_vco_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static struct div_nmp plld_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .divn_shift = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) { 12000000, 594000000, 99, 1, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) { 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static struct tegra_clk_pll_params pll_d_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .cf_max = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .vco_min = 750000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .vco_max = 1500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .base_reg = PLLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .misc_reg = PLLD_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .iddq_reg = PLLD_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .iddq_bit_idx = PLLD_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .round_p_to_pdiv = pll_expo_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .pdiv_tohw = pll_expo_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .div_nmp = &plld_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .sdm_din_reg = PLLD_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .sdm_din_mask = PLLA_SDM_DIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .sdm_ctrl_reg = PLLD_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .ext_misc_reg[0] = PLLD_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .ext_misc_reg[1] = PLLD_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .mdiv_default = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .set_defaults = tegra210_plld_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .set_gain = tegra210_clk_pll_set_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .adjust_vco = tegra210_clk_adjust_vco_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) { 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* s/w policy, always tegra_pll_ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static struct tegra_clk_pll_params pll_d2_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .cf_max = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .vco_min = 750000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .vco_max = 1500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .base_reg = PLLD2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .misc_reg = PLLD2_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .iddq_reg = PLLD2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .iddq_bit_idx = PLLSS_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .sdm_din_reg = PLLD2_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .sdm_din_mask = PLLA_SDM_DIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .sdm_ctrl_reg = PLLD2_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* disable spread-spectrum for pll_d2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .ssc_ctrl_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .ssc_ctrl_en_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .div_nmp = &pllss_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .ext_misc_reg[0] = PLLD2_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .ext_misc_reg[1] = PLLD2_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .ext_misc_reg[2] = PLLD2_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .ext_misc_reg[3] = PLLD2_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .mdiv_default = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .freq_table = tegra210_pll_d2_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .set_defaults = tegra210_plld2_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .set_gain = tegra210_clk_pll_set_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .adjust_vco = tegra210_clk_adjust_vco_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) { 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static struct tegra_clk_pll_params pll_dp_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .cf_max = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .vco_min = 750000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .vco_max = 1500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .base_reg = PLLDP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .misc_reg = PLLDP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .iddq_reg = PLLDP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .iddq_bit_idx = PLLSS_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .sdm_din_reg = PLLDP_SS_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .sdm_din_mask = PLLA_SDM_DIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .sdm_ctrl_reg = PLLDP_SS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .ssc_ctrl_reg = PLLDP_SS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .div_nmp = &pllss_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .ext_misc_reg[0] = PLLDP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .ext_misc_reg[1] = PLLDP_SS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .ext_misc_reg[2] = PLLDP_SS_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .ext_misc_reg[3] = PLLDP_SS_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .max_p = PLL_QLIN_PDIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .mdiv_default = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .freq_table = pll_dp_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .set_defaults = tegra210_plldp_set_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .calc_rate = tegra210_pll_fixed_mdiv_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .set_gain = tegra210_clk_pll_set_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .adjust_vco = tegra210_clk_adjust_vco_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static struct div_nmp pllu_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .divp_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .divp_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) { 12000000, 480000000, 40, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) { 38400000, 480000000, 25, 2, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) static struct tegra_clk_pll_params pll_u_vco_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .input_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .cf_min = 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .vco_min = 350000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .base_reg = PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .misc_reg = PLLU_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .iddq_reg = PLLU_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .iddq_bit_idx = PLLU_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .ext_misc_reg[0] = PLLU_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .ext_misc_reg[1] = PLLU_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .round_p_to_pdiv = pll_qlin_p_to_pdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .pdiv_tohw = pll_qlin_pdiv_to_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .div_nmp = &pllu_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .freq_table = pll_u_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) struct utmi_clk_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* Oscillator Frequency in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) u32 osc_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) /* UTMIP PLL Enable Delay Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) u8 enable_delay_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) /* UTMIP PLL Stable count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) u16 stable_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* UTMIP PLL Active delay count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) u8 active_delay_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* UTMIP PLL Xtal frequency count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) u16 xtal_freq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static const struct utmi_clk_param utmi_parameters[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .osc_frequency = 38400000, .enable_delay_count = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .stable_count = 0x0, .active_delay_count = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .xtal_freq_count = 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .osc_frequency = 13000000, .enable_delay_count = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .stable_count = 0x33, .active_delay_count = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .xtal_freq_count = 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .osc_frequency = 19200000, .enable_delay_count = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .stable_count = 0x4b, .active_delay_count = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .xtal_freq_count = 0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .osc_frequency = 12000000, .enable_delay_count = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .stable_count = 0x2f, .active_delay_count = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .xtal_freq_count = 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .osc_frequency = 26000000, .enable_delay_count = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .stable_count = 0x66, .active_delay_count = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .xtal_freq_count = 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .osc_frequency = 16800000, .enable_delay_count = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .stable_count = 0x41, .active_delay_count = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .xtal_freq_count = 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) [tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) [tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static struct tegra_devclk devclks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static struct tegra_audio_clk_info tegra210_audio_plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static const char * const aclk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) "clk_m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) TEGRA210_CLK_HOST1X};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) TEGRA210_CLK_XUSB_DEV };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) TEGRA210_CLK_XUSB_SS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) TEGRA210_CLK_XUSB_SS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) TEGRA210_CLK_PLL_D };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) TEGRA210_CLK_D_AUDIO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) [TEGRA_POWERGATE_VENC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .handle_lvl2_ovr = tegra210_venc_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .num_clks = ARRAY_SIZE(venc_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .clk_init_data = venc_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) [TEGRA_POWERGATE_SATA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .lvl2_offset = LVL2_CLK_GATE_OVRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) [TEGRA_POWERGATE_MPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .lvl2_offset = LVL2_CLK_GATE_OVRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .lvl2_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) [TEGRA_POWERGATE_SOR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .num_clks = ARRAY_SIZE(sor_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .clk_init_data = sor_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .lvl2_offset = LVL2_CLK_GATE_OVRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .lvl2_mask = BIT(1) | BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) [TEGRA_POWERGATE_DIS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .handle_lvl2_ovr = tegra210_disp_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .num_clks = ARRAY_SIZE(disp_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .clk_init_data = disp_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) [TEGRA_POWERGATE_DISB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .num_clks = ARRAY_SIZE(disp_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .clk_init_data = disp_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .lvl2_offset = LVL2_CLK_GATE_OVRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .lvl2_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) [TEGRA_POWERGATE_XUSBA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) .clk_init_data = xusba_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .lvl2_offset = LVL2_CLK_GATE_OVRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .lvl2_mask = BIT(30) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) [TEGRA_POWERGATE_XUSBB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .clk_init_data = xusbb_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .lvl2_offset = LVL2_CLK_GATE_OVRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .lvl2_mask = BIT(30) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) [TEGRA_POWERGATE_XUSBC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .clk_init_data = xusbc_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .lvl2_offset = LVL2_CLK_GATE_OVRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .lvl2_mask = BIT(30) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) [TEGRA_POWERGATE_VIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .num_clks = ARRAY_SIZE(vic_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .clk_init_data = vic_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .handle_lvl2_ovr = tegra210_vic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) [TEGRA_POWERGATE_NVDEC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) .clk_init_data = nvdec_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .lvl2_offset = LVL2_CLK_GATE_OVRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .lvl2_mask = BIT(9) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) [TEGRA_POWERGATE_NVJPG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .clk_init_data = nvjpg_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .lvl2_offset = LVL2_CLK_GATE_OVRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) .lvl2_mask = BIT(9) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) [TEGRA_POWERGATE_AUD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .num_clks = ARRAY_SIZE(ape_slcg_clkids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .clk_init_data = ape_slcg_clkids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .handle_lvl2_ovr = tegra210_ape_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) [TEGRA_POWERGATE_VE2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .handle_lvl2_ovr = tegra210_generic_mbist_war,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .lvl2_offset = LVL2_CLK_GATE_OVRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .lvl2_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) int tegra210_clk_handle_mbist_war(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) struct tegra210_domain_mbist_war *mbist_war;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) WARN(1, "unknown domain id in MBIST WAR handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) mbist_war = &tegra210_pg_mbist_war[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) if (!mbist_war->handle_lvl2_ovr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (mbist_war->num_clks && !mbist_war->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) mutex_lock(&lvl2_ovr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) mbist_war->handle_lvl2_ovr(mbist_war);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) mutex_unlock(&lvl2_ovr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) void tegra210_put_utmipll_in_iddq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) void tegra210_put_utmipll_out_iddq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static void tegra210_utmi_param_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) if (osc_freq == utmi_parameters[i].osc_frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) if (i >= ARRAY_SIZE(utmi_parameters)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) osc_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /* Program UTMIP PLL stable and active counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) reg |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* Program UTMIP PLL delay and oscillator frequency counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) reg |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) reg |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* Remove power downs from UTMIP PLL control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* Setup HW control of UTMIPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) /* Enable HW control UTMIPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) static int tegra210_enable_pllu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) struct tegra_clk_pll_freq_table *fentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) struct tegra_clk_pll pllu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (fentry->input_rate == pll_ref_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) if (!fentry->input_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /* clear IDDQ bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) pllu.params = &pll_u_vco_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) reg &= ~BIT(pllu.params->iddq_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) fence_udelay(5, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) reg = readl_relaxed(clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) reg &= ~GENMASK(20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) reg |= fentry->m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) reg |= fentry->n << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) reg |= fentry->p << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) writel(reg, clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) reg |= PLL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) writel(reg, clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) * During clocks resume, same PLLU init and enable sequence get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) * executed. So, readx_poll_timeout_atomic can't be used here as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) * uses ktime_get() and timekeeping resume doesn't happen by that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) * time. So, using tegra210_wait_for_mask for PLL LOCK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) pr_err("Timed out waiting for PLL_U to lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) static int tegra210_init_pllu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) tegra210_pllu_set_defaults(&pll_u_vco_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) /* skip initialization when pllu is in hw controlled mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) reg = readl_relaxed(clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) if (reg & PLLU_BASE_OVERRIDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) if (!(reg & PLL_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) err = tegra210_enable_pllu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /* enable hw controlled mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) reg = readl_relaxed(clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) reg &= ~PLLU_BASE_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) writel(reg, clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) fence_udelay(1, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) reg = readl_relaxed(clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) reg &= ~PLLU_BASE_CLKENABLE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) writel_relaxed(reg, clk_base + PLLU_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) /* enable UTMIPLL hw control if not yet done by the bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) tegra210_utmi_param_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) * The SOR hardware blocks are driven by two clocks: a module clock that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) * used to access registers and a pixel clock that is sourced from the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) * pixel clock that also drives the head attached to the SOR. The module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) * clock is typically called sorX (with X being the SOR instance) and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) * pixel clock is called sorX_out. The source for the SOR pixel clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) * referred to as the "parent" clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) * On Tegra186 and newer, clocks are provided by the BPMP. Unfortunately the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) * BPMP implementation for the SOR clocks doesn't exactly match the above in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) * some aspects. For example, the SOR module is really clocked by the pad or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * sor_safe clocks, but BPMP models the sorX clock as being sourced by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * pixel clocks. Conversely the sorX_out clock is sourced by the sor_safe or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) * pad clocks on BPMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) * In order to allow the display driver to deal with all SoC generations in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) * a unified way, implement the BPMP semantics in this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) static const char * const sor0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) "pll_d_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static const char * const sor0_out_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) "sor_safe", "sor0_pad_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static const char * const sor1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) static const struct clk_div_table mc_div_table_tegra210[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) { .val = 1, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) { .val = 2, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) { .val = 3, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) { .val = 0, .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static void tegra210_clk_register_mc(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) clk = clk_register_divider_table(NULL, name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) clk_base + CLK_SOURCE_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) 15, 2, CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) mc_div_table_tegra210, &emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) clks[TEGRA210_CLK_MC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) static const char * const sor1_out_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * the sor1_pad_clkout parent appears twice in the list below. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) * merely to support clk_get_parent() if firmware happened to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) * these bits to 0b11. While not an invalid setting, code should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) * always set the bits to 0b01 to select sor1_pad_clkout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) "sor_safe", "sor1_pad_clkout", "sor1_out", "sor1_pad_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static struct tegra_periph_init_data tegra210_periph[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) * On Tegra210, the sor0 clock doesn't have a mux it bitfield 31:29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) * but it is hardwired to the pll_d_out0 clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) CLK_SOURCE_SOR0, 29, 0x0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) 0, 182, 0, tegra_clk_sor0, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) &sor0_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) NULL, 0, &sor0_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) TEGRA_DIVIDER_ROUND_UP, 183, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) tegra_clk_sor1, sor1_parents_idx, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) &sor1_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) TEGRA_INIT_DATA_TABLE("sor1_out", NULL, NULL, sor1_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) CLK_SOURCE_SOR1, 14, 0x3, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) 0, 0, TEGRA_PERIPH_NO_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) tegra_clk_sor1_out, NULL, 0, &sor1_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) static const char * const la_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) static struct tegra_clk_periph tegra210_la =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) static __init void tegra210_periph_clk_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) void __iomem *pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) /* xusb_ss_div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) 1, 17, 222);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) clks[TEGRA210_CLK_SOR_SAFE] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) 1, 17, 181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) clks[TEGRA210_CLK_DPAUX] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) 1, 17, 207);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) clks[TEGRA210_CLK_DPAUX1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /* pll_d_dsi_out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) /* dsia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) clk_base, 0, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) clks[TEGRA210_CLK_DSIA] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /* dsib */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) clk_base, 0, 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) clks[TEGRA210_CLK_DSIB] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) /* csi_tpg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) clk = clk_register_gate(NULL, "csi_tpg", "pll_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) 23, 0, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) clk_register_clkdev(clk, "csi_tpg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) clks[TEGRA210_CLK_CSI_TPG] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) /* la */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) clk = tegra_clk_register_periph("la", la_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) CLK_SOURCE_LA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) clks[TEGRA210_CLK_LA] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) /* cml0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) 0, 0, &pll_e_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) clk_register_clkdev(clk, "cml0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) clks[TEGRA210_CLK_CML0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) /* cml1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) 1, 0, &pll_e_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) clk_register_clkdev(clk, "cml1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) clks[TEGRA210_CLK_CML1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) clk = tegra_clk_register_super_clk("aclk", aclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) clks[TEGRA210_CLK_ACLK] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) CLK_SOURCE_SDMMC2, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) TEGRA_DIVIDER_ROUND_UP, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) clks[TEGRA210_CLK_SDMMC2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) CLK_SOURCE_SDMMC4, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) TEGRA_DIVIDER_ROUND_UP, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) clks[TEGRA210_CLK_SDMMC4] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) struct tegra_periph_init_data *init = &tegra210_periph[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) struct clk **clkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (!clkp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) pr_warn("clock %u not found\n", init->clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) clk = tegra_clk_register_periph_data(clk_base, init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) *clkp = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) /* emc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) clk = tegra210_clk_register_emc(np, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) clks[TEGRA210_CLK_EMC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) /* mc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) tegra210_clk_register_mc("mc", "emc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) static void __init tegra210_pll_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) void __iomem *pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) /* PLLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) pmc, 0, &pll_c_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) if (!WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) clk_register_clkdev(clk, "pll_c", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) clks[TEGRA210_CLK_PLL_C] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) /* PLLC_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) clk_base + PLLC_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) clk_register_clkdev(clk, "pll_c_out1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) /* PLLC_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) clk_register_clkdev(clk, "pll_c_ud", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) clks[TEGRA210_CLK_PLL_C_UD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) /* PLLC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) pmc, 0, &pll_c2_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) clk_register_clkdev(clk, "pll_c2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) clks[TEGRA210_CLK_PLL_C2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* PLLC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) pmc, 0, &pll_c3_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) clk_register_clkdev(clk, "pll_c3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) clks[TEGRA210_CLK_PLL_C3] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) /* PLLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) CLK_SET_RATE_GATE, &pll_m_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) clk_register_clkdev(clk, "pll_m", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) clks[TEGRA210_CLK_PLL_M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) /* PLLMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) CLK_SET_RATE_GATE, &pll_mb_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) clk_register_clkdev(clk, "pll_mb", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) clks[TEGRA210_CLK_PLL_MB] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) /* PLLM_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) clk_register_clkdev(clk, "pll_m_ud", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) clks[TEGRA210_CLK_PLL_M_UD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) /* PLLMB_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) clk_register_clkdev(clk, "pll_mb_ud", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) clks[TEGRA210_CLK_PLL_MB_UD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) /* PLLP_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) clks[TEGRA210_CLK_PLL_P_UD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) /* PLLU_VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) if (!tegra210_init_pllu()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) 480*1000*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) clk_register_clkdev(clk, "pll_u_vco", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) clks[TEGRA210_CLK_PLL_U] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) /* PLLU_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) clk_base + PLLU_BASE, 16, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) pll_vco_post_div_table, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) clk_register_clkdev(clk, "pll_u_out", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) clks[TEGRA210_CLK_PLL_U_OUT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) /* PLLU_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) clk_base + PLLU_OUTA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) 8, 8, 1, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) clk_base + PLLU_OUTA, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) CLK_SET_RATE_PARENT, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) clk_register_clkdev(clk, "pll_u_out1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) /* PLLU_OUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) clk_base + PLLU_OUTA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) 24, 8, 1, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) clk_base + PLLU_OUTA, 17, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) CLK_SET_RATE_PARENT, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) clk_register_clkdev(clk, "pll_u_out2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) /* PLLU_480M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) 22, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) clk_register_clkdev(clk, "pll_u_480M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) clks[TEGRA210_CLK_PLL_U_480M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) /* PLLU_60M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) 23, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) clk_register_clkdev(clk, "pll_u_60M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) clks[TEGRA210_CLK_PLL_U_60M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) /* PLLU_48M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) 25, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) clk_register_clkdev(clk, "pll_u_48M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) clks[TEGRA210_CLK_PLL_U_48M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) /* PLLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) &pll_d_params, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) clk_register_clkdev(clk, "pll_d", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) clks[TEGRA210_CLK_PLL_D] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) /* PLLD_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) clk_register_clkdev(clk, "pll_d_out0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) /* PLLRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) &pll_re_vco_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) &pll_re_lock, pll_ref_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) clk_register_clkdev(clk, "pll_re_vco", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) clk_base + PLLRE_BASE, 16, 5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) pll_vco_post_div_table, &pll_re_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) clk_register_clkdev(clk, "pll_re_out", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) clk_base + PLLRE_OUT1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) clk_base + PLLRE_OUT1, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) /* PLLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) clk_base, 0, &pll_e_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) clk_register_clkdev(clk, "pll_e", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) clks[TEGRA210_CLK_PLL_E] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) /* PLLC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) 0, &pll_c4_vco_params, NULL, pll_ref_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) clk_register_clkdev(clk, "pll_c4_vco", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) clks[TEGRA210_CLK_PLL_C4] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) /* PLLC4_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) clk_base + PLLC4_BASE, 19, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) pll_vco_post_div_table, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) clk_register_clkdev(clk, "pll_c4_out0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) /* PLLC4_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) CLK_SET_RATE_PARENT, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) clk_register_clkdev(clk, "pll_c4_out1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) /* PLLC4_OUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) CLK_SET_RATE_PARENT, 1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) clk_register_clkdev(clk, "pll_c4_out2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) /* PLLC4_OUT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) clk_base + PLLC4_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) clk_register_clkdev(clk, "pll_c4_out3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) /* PLLDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) 0, &pll_dp_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) clk_register_clkdev(clk, "pll_dp", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) clks[TEGRA210_CLK_PLL_DP] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) /* PLLD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) 0, &pll_d2_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) clk_register_clkdev(clk, "pll_d2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) clks[TEGRA210_CLK_PLL_D2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) /* PLLD2_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) clk_register_clkdev(clk, "pll_d2_out0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) /* PLLP_OUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) clk_register_clkdev(clk, "pll_p_out2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) /* Tegra210 CPU clock and reset control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) static void tegra210_wait_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) static void tegra210_disable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) /* flow controller would take care in the power sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) #define car_writel(_val, _base, _off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) static u32 cpu_softrst_ctx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) static int tegra210_clk_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) clk_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) * Save the bootloader configured clock registers SPARE_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) tegra_clk_periph_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) static void tegra210_clk_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) tegra_clk_osc_resume(clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) * Restore the bootloader configured clock registers SPARE_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) * Tegra clock programming sequence recommends peripheral clock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) * be enabled prior to changing its clock source and divider to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) * prevent glitchless frequency switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) * So, enable all peripheral clocks before restoring their source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) * and dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) /* wait for all writes to happen to have all the clocks enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) fence_udelay(2, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) /* restore PLLs and all peripheral clock rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) tegra210_init_pllu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) clk_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) /* restore saved context of peripheral clocks and reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) tegra_clk_periph_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) static void tegra210_cpu_clock_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) /* switch coresite to clk_m, save off original source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) tegra210_cpu_clk_sctx.clk_csite_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) readl(clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) static void tegra210_cpu_clock_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) writel(tegra210_cpu_clk_sctx.clk_csite_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) static struct syscore_ops tegra_clk_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) .suspend = tegra210_clk_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) .resume = tegra210_clk_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) .wait_for_reset = tegra210_wait_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .disable_clock = tegra210_disable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) .suspend = tegra210_cpu_clock_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) .resume = tegra210_cpu_clock_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) static const struct of_device_id pmc_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) { .compatible = "nvidia,tegra210-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) static struct tegra_clk_init_table init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) /* TODO find a way to enable this on-demand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) /* This MUST be the last entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) * Program an initial clock rate and enable or disable clocks needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) * called by assigning a pointer to it to tegra_clk_apply_init_table -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) * this will be called as an arch_initcall. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) static void __init tegra210_clock_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) * tegra210_car_barrier - wait for pending writes to the CAR to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) * Wait for any outstanding writes to the CAR MMIO space from this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) * to complete before continuing execution. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) static void tegra210_car_barrier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) * Assert the reset line of the DFLL's DVCO. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) static void tegra210_clock_assert_dfll_dvco_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) v = readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) v |= (1 << DVFS_DFLL_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) writel_relaxed(v, clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) tegra210_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) * operate. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) static void tegra210_clock_deassert_dfll_dvco_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) v = readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) writel_relaxed(v, clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) tegra210_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) static int tegra210_reset_assert(unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) if (id == TEGRA210_RST_DFLL_DVCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) tegra210_clock_assert_dfll_dvco_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) else if (id == TEGRA210_RST_ADSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) writel(GENMASK(26, 21) | BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) static int tegra210_reset_deassert(unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) if (id == TEGRA210_RST_DFLL_DVCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) tegra210_clock_deassert_dfll_dvco_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) else if (id == TEGRA210_RST_ADSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) * a delay of 5us ensures that it's at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) * 6 * adsp_cpu_cycle_period long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) writel(GENMASK(26, 22) | BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) static void tegra210_mbist_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) struct clk_bulk_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) if (!num_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) if (WARN_ON(!clk_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) tegra210_pg_mbist_war[i].clks = clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) for (j = 0; j < num_clks; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) struct clk *clk = clks[clk_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) tegra210_pg_mbist_war[i].clks = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) clk_data[j].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * tegra210_clock_init - Tegra210-specific clock initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) * @np: struct device_node * of the DT node for the SoC CAR IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) * Register most SoC clocks for the Tegra210 system-on-chip. Intended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) * to be called by the OF init code when a DT node with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) * "nvidia,tegra210-car" string is encountered, and declared with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) * CLK_OF_DECLARE. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) static void __init tegra210_clock_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) u32 value, clk_m_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) pr_err("ioremap tegra210 CAR failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) node = of_find_matching_node(NULL, pmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) pr_err("Failed to find pmc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) pmc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) if (!pmc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) pr_err("Can't map pmc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) if (!ahub_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) pr_err("ioremap tegra210 APE failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) if (!dispa_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) pr_err("ioremap tegra210 DISPA failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) if (!vic_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) pr_err("ioremap tegra210 VIC failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) TEGRA210_CAR_BANK_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) ARRAY_SIZE(tegra210_input_freq), clk_m_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) &osc_freq, &pll_ref_freq) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) tegra_fixed_clk_init(tegra210_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) tegra210_pll_init(clk_base, pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) tegra210_periph_clk_init(np, clk_base, pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) tegra210_audio_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) ARRAY_SIZE(tegra210_audio_plls), 24576000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) /* For Tegra210, PLLD is the only source for DSIA & DSIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) value = readl(clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) value &= ~BIT(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) writel(value, clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) &pll_x_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) tegra_init_special_resets(2, tegra210_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) tegra210_reset_deassert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) tegra_add_of_provider(np, of_clk_src_onecell_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) tegra210_mbist_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) tegra_cpu_car_ops = &tegra210_cpu_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) register_syscore_ops(&tegra_clk_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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