^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_SOURCE_EMC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_SRC_PLLM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_SRC_PLLC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_SRC_PLLP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_SRC_CLK_M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_SRC_PLLM_UD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_SRC_PLLMB_UD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_SRC_PLLMB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_SRC_PLLP_UD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct tegra210_clk_emc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct tegra210_clk_emc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *parents[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline struct tegra210_clk_emc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) to_tegra210_clk_emc(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return container_of(hw, struct tegra210_clk_emc, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *tegra210_clk_emc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb_ud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "pll_mb", "pll_p_ud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static u8 tegra210_clk_emc_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) value = readl_relaxed(emc->regs + CLK_SOURCE_EMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned long tegra210_clk_emc_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 value, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * CCF assumes that neither the parent nor its rate will change during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * ->set_rate(), so the parent rate passed in here was cached from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * parent before the ->set_rate() call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * This can lead to wrong results being reported for the EMC clock if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * the parent and/or parent rate have changed as part of the EMC rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * change sequence. Fix this by overriding the parent clock with what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * we know to be the correct value after the rate change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) value = readl_relaxed(emc->regs + CLK_SOURCE_EMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) div += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return DIV_ROUND_UP(parent_rate * 2, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static long tegra210_clk_emc_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct tegra210_clk_emc_provider *provider = emc->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!provider || !provider->configs || provider->num_configs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return clk_hw_get_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (i = 0; i < provider->num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (provider->configs[i].rate >= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return provider->configs[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return provider->configs[i - 1].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const char *name = clk_hw_get_name(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* XXX implement cache? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return __clk_lookup(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int tegra210_clk_emc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct tegra210_clk_emc_provider *provider = emc->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct tegra210_clk_emc_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct device *dev = provider->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct clk_hw *old, *new, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 old_idx, new_idx, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!provider->configs || provider->num_configs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < provider->num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (provider->configs[i].rate >= rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) config = &provider->configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (i == provider->num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) config = &provider->configs[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) old_idx = tegra210_clk_emc_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) new_idx = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) old = clk_hw_get_parent_by_index(hw, old_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) new = clk_hw_get_parent_by_index(hw, new_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* if the rate has changed... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (config->parent_rate != clk_hw_get_rate(old)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* ... but the clock source remains the same ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (new_idx == old_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* ... switch to the alternative clock source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) switch (new_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case CLK_SRC_PLLM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) new_idx = CLK_SRC_PLLMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case CLK_SRC_PLLM_UD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) new_idx = CLK_SRC_PLLMB_UD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case CLK_SRC_PLLMB_UD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) new_idx = CLK_SRC_PLLM_UD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case CLK_SRC_PLLMB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) new_idx = CLK_SRC_PLLM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * This should never happen because we can't deal with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (WARN_ON(new_idx == old_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) new = clk_hw_get_parent_by_index(hw, new_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) index = new_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) parent = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) index = old_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) parent = old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk = tegra210_clk_emc_find_parent(emc, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(dev, "failed to get parent clock for index %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) index, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* set the new parent clock to the required rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (clk_get_rate(clk) != config->parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err = clk_set_rate(clk, config->parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(dev, "failed to set rate %lu Hz for %pC: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) config->parent_rate, clk, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* enable the new parent clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (parent != old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(dev, "failed to enable parent clock %pC: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) clk, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* update the EMC source configuration to reflect the new parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) config->value &= ~CLK_SOURCE_EMC_2X_CLK_SRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) config->value |= FIELD_PREP(CLK_SOURCE_EMC_2X_CLK_SRC, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Finally, switch the EMC programming with both old and new parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * clocks enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) err = provider->set_rate(dev, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(dev, "failed to set EMC rate to %lu Hz: %d\n", rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * If we're unable to switch to the new EMC frequency, we no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * longer need the new parent to be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (parent != old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* reparent to new parent clock and disable the old parent clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (parent != old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk = tegra210_clk_emc_find_parent(emc, old_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "failed to get parent clock for index %u: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) old_idx, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_hw_reparent(hw, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct clk_ops tegra210_clk_emc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .get_parent = tegra210_clk_emc_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .recalc_rate = tegra210_clk_emc_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .round_rate = tegra210_clk_emc_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .set_rate = tegra210_clk_emc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct clk *tegra210_clk_register_emc(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct tegra210_clk_emc *emc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) emc = kzalloc(sizeof(*emc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) emc->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) init.name = "emc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) init.ops = &tegra210_clk_emc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) init.flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) init.parent_names = tegra210_clk_emc_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) init.num_parents = ARRAY_SIZE(tegra210_clk_emc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) emc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clk = clk_register(NULL, &emc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) kfree(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int tegra210_clk_emc_attach(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct tegra210_clk_emc_provider *provider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct clk_hw *hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct device *dev = provider->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!try_module_get(provider->owner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (i = 0; i < provider->num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct tegra210_clk_emc_config *config = &provider->configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bool same_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 div, src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, config->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* do basic sanity checking on the EMC timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (div & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_err(dev, "invalid odd divider %u for rate %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) div, config->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) same_freq = config->value & CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (same_freq != config->same_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "ambiguous EMC to MC ratio for rate %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) config->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) parent = clk_hw_get_parent_by_index(hw, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) config->parent = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (src == CLK_SRC_PLLM || src == CLK_SRC_PLLM_UD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) config->parent_rate = config->rate * (1 + div / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long rate = config->rate * (1 + div / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) config->parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (config->parent_rate != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "rate %lu Hz does not match input\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) config->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) emc->provider = provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) module_put(provider->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) EXPORT_SYMBOL_GPL(tegra210_clk_emc_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void tegra210_clk_emc_detach(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct tegra210_clk_emc *emc = to_tegra210_clk_emc(__clk_get_hw(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) module_put(emc->provider->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) emc->provider = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) EXPORT_SYMBOL_GPL(tegra210_clk_emc_detach);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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