^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/tegra20-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MISC_CLK_ENB 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OSC_CTRL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OSC_FREQ_DET 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OSC_FREQ_DET_TRIG (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OSC_FREQ_DET_STATUS 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OSC_FREQ_DET_BUSY (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OSC_FREQ_DET_CNT_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA20_CLK_PERIPH_BANKS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLLS_BASE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLLS_MISC 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLLC_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLLC_MISC 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLLM_BASE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLLM_MISC 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PLLP_BASE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLLP_MISC 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLLA_BASE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLLA_MISC 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLLU_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLLU_MISC 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLLD_BASE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLD_MISC 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLLX_MISC 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLLE_BASE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLE_MISC 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLL_BASE_LOCK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLE_MISC_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLL_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLLDU_MISC_LOCK_ENABLE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLLE_MISC_LOCK_ENABLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLLC_OUT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLLM_OUT 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLP_OUTA 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLLP_OUTB 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLLA_OUT 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CCLK_BURST_POLICY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUPER_CCLK_DIVIDER 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCLK_BURST_POLICY 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUPER_SCLK_DIVIDER 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_SYSTEM_RATE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CCLK_BURST_POLICY_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CCLK_RUN_POLICY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CCLK_IDLE_POLICY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CCLK_IDLE_POLICY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CCLK_RUN_POLICY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CCLK_BURST_POLICY_PLLX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_SOURCE_I2S1 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_SOURCE_I2S2 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_SOURCE_PWM 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_SOURCE_SPI 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_SOURCE_XIO 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_SOURCE_TWC 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_SOURCE_IDE 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_SOURCE_HDMI 0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_SOURCE_DISP1 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_SOURCE_DISP2 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_SOURCE_CSITE 0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_SOURCE_I2C1 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_SOURCE_I2C2 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_SOURCE_I2C3 0x1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_SOURCE_DVC 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_SOURCE_UARTA 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_SOURCE_UARTB 0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_SOURCE_UARTC 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_SOURCE_UARTD 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_SOURCE_UARTE 0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_SOURCE_EMC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AUDIO_SYNC_CLK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Tegra CPU clock and reset control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CPU_RESET(cpu) (0x1111ul << (cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct cpu_clk_suspend_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 pllx_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 pllx_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 cpu_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 clk_csite_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 cclk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } tegra20_cpu_clk_sctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) _gate_flags, _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) _clk_num, _gate_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) _mux_shift, _mux_width, _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) _clk_num, _gate_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) _clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 12000000, 600000000, 600, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 13000000, 600000000, 600, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 19200000, 600000000, 500, 16, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 26000000, 600000000, 600, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 12000000, 666000000, 666, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 13000000, 666000000, 666, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 19200000, 666000000, 555, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 26000000, 666000000, 666, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 12000000, 600000000, 600, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 13000000, 600000000, 600, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 19200000, 600000000, 375, 12, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 26000000, 600000000, 600, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 12000000, 216000000, 432, 12, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 13000000, 216000000, 432, 13, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 19200000, 216000000, 90, 4, 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 26000000, 216000000, 432, 26, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 12000000, 432000000, 432, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 13000000, 432000000, 432, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 19200000, 432000000, 90, 4, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 26000000, 432000000, 432, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 28800000, 56448000, 49, 25, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 28800000, 73728000, 64, 25, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 28800000, 24000000, 5, 6, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 12000000, 216000000, 216, 12, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 13000000, 216000000, 216, 13, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 19200000, 216000000, 135, 12, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 26000000, 216000000, 216, 26, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 12000000, 594000000, 594, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 13000000, 594000000, 594, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 19200000, 594000000, 495, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 26000000, 594000000, 594, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 12000000, 1000000000, 1000, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 13000000, 1000000000, 1000, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 19200000, 1000000000, 625, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 26000000, 1000000000, 1000, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 12000000, 480000000, 960, 12, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 13000000, 480000000, 960, 13, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 19200000, 480000000, 200, 4, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 26000000, 480000000, 960, 26, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 12000000, 1000000000, 1000, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 13000000, 1000000000, 1000, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 19200000, 1000000000, 625, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 26000000, 1000000000, 1000, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* 912 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 12000000, 912000000, 912, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 13000000, 912000000, 912, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 19200000, 912000000, 760, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 26000000, 912000000, 912, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 816 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 12000000, 816000000, 816, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 13000000, 816000000, 816, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 19200000, 816000000, 680, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 26000000, 816000000, 816, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* 760 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 12000000, 760000000, 760, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 13000000, 760000000, 760, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 19200000, 760000000, 950, 24, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 26000000, 760000000, 760, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* 750 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 12000000, 750000000, 750, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 13000000, 750000000, 750, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 19200000, 750000000, 625, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 26000000, 750000000, 750, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* 608 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 12000000, 608000000, 608, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 13000000, 608000000, 608, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 19200000, 608000000, 380, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 26000000, 608000000, 608, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* 456 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 12000000, 456000000, 456, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 13000000, 456000000, 456, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 19200000, 456000000, 380, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 26000000, 456000000, 456, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* 312 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 12000000, 312000000, 312, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 13000000, 312000000, 312, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 19200000, 312000000, 260, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 26000000, 312000000, 312, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct pdiv_map plle_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .pdiv = 1, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 12000000, 100000000, 200, 24, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* PLL parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct tegra_clk_pll_params pll_c_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .base_reg = PLLC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .misc_reg = PLLC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .freq_table = pll_c_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct tegra_clk_pll_params pll_m_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .base_reg = PLLM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .misc_reg = PLLM_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .freq_table = pll_m_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct tegra_clk_pll_params pll_p_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .base_reg = PLLP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .misc_reg = PLLP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .freq_table = pll_p_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .fixed_rate = 216000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct tegra_clk_pll_params pll_a_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .base_reg = PLLA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .misc_reg = PLLA_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .freq_table = pll_a_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct tegra_clk_pll_params pll_d_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .vco_min = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .base_reg = PLLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .misc_reg = PLLD_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct pdiv_map pllu_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { .pdiv = 1, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { .pdiv = 2, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct tegra_clk_pll_params pll_u_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .vco_min = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .vco_max = 960000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .base_reg = PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .misc_reg = PLLU_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .pdiv_tohw = pllu_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .freq_table = pll_u_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct tegra_clk_pll_params pll_x_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .vco_min = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .base_reg = PLLX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .misc_reg = PLLX_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .freq_table = pll_x_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .post_rate_change = tegra_cclk_post_pllx_rate_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct tegra_clk_pll_params pll_e_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .input_max = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .cf_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .cf_max = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .vco_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .vco_max = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .base_reg = PLLE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .misc_reg = PLLE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .lock_mask = PLLE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .lock_delay = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pdiv_tohw = plle_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .freq_table = pll_e_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .fixed_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct tegra_devclk devclks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static unsigned long tegra20_clk_measure_input_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long input_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) switch (auto_clk_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case OSC_CTRL_OSC_FREQ_12MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) input_freq = 12000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case OSC_CTRL_OSC_FREQ_13MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) input_freq = 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case OSC_CTRL_OSC_FREQ_19_2MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) input_freq = 19200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case OSC_CTRL_OSC_FREQ_26MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) input_freq = 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pr_err("Unexpected clock autodetect value %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) auto_clk_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return input_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static unsigned int tegra20_get_pll_ref_div(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) OSC_CTRL_PLL_REF_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) switch (pll_ref_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case OSC_CTRL_PLL_REF_DIV_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case OSC_CTRL_PLL_REF_DIV_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case OSC_CTRL_PLL_REF_DIV_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) pr_err("Invalid pll ref divider %d\n", pll_ref_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void tegra20_pll_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* PLLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &pll_c_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clks[TEGRA20_CLK_PLL_C] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* PLLC_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* PLLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) CLK_SET_RATE_GATE, &pll_m_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) clks[TEGRA20_CLK_PLL_M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* PLLM_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) clk_base + PLLM_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* PLLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &pll_x_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) clks[TEGRA20_CLK_PLL_X] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* PLLU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &pll_u_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) clks[TEGRA20_CLK_PLL_U] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* PLLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &pll_d_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) clks[TEGRA20_CLK_PLL_D] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* PLLD_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* PLLA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &pll_a_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) clks[TEGRA20_CLK_PLL_A] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* PLLA_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* PLLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 0, &pll_e_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) clks[TEGRA20_CLK_PLL_E] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "pll_p", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "pll_p_out3", "clk_d", "pll_x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "pll_p_out3", "pll_p_out2", "clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "clk_32k", "pll_m_out1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void tegra20_super_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* CCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) clk = tegra_clk_register_super_cclk("cclk", cclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) clks[TEGRA20_CLK_CCLK] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) clk = tegra_clk_register_super_mux("sclk", sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ARRAY_SIZE(sclk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clks[TEGRA20_CLK_SCLK] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* twd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) clks[TEGRA20_CLK_TWD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "pll_a_out0", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "unused" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void __init tegra20_audio_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clk = clk_register_mux(NULL, "audio_mux", audio_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ARRAY_SIZE(audio_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk_base + AUDIO_SYNC_CLK, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) CLK_GATE_SET_TO_DISABLE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clks[TEGRA20_CLK_AUDIO] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* audio_2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) CLK_SET_RATE_PARENT, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) TEGRA_PERIPH_NO_RESET, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) CLK_SET_RATE_PARENT, 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) clks[TEGRA20_CLK_AUDIO_2X] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "clk_32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "clk_m" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static struct tegra_periph_init_data tegra_periph_clk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void __init tegra20_periph_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct tegra_periph_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* ac97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) TEGRA_PERIPH_ON_APB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) clk_base, 0, 3, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) clks[TEGRA20_CLK_AC97] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* emc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) clks[TEGRA20_CLK_EMC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) clks[TEGRA20_CLK_MC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* dsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 48, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) clk_register_clkdev(clk, NULL, "dsi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) clks[TEGRA20_CLK_DSI] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* pex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) clks[TEGRA20_CLK_PEX] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* dev1 OSC divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clk_register_divider(NULL, "dev1_osc_div", "clk_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 0, clk_base + MISC_CLK_ENB, 22, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* dev2 OSC divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clk_register_divider(NULL, "dev2_osc_div", "clk_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 0, clk_base + MISC_CLK_ENB, 20, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* cdev1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) clk_base, 0, 94, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) clks[TEGRA20_CLK_CDEV1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* cdev2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) clk_base, 0, 93, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clks[TEGRA20_CLK_CDEV2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) data = &tegra_periph_clk_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clk = tegra_clk_register_periph_data(clk_base, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) clks[data->clk_id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) data = &tegra_periph_nodiv_clk_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) clk = tegra_clk_register_periph_nodiv(data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) data->p.parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) data->num_parents, &data->periph,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) clk_base, data->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) clks[data->clk_id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static void __init tegra20_osc_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned long input_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned int pll_ref_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) input_freq = tegra20_clk_measure_input_freq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* clk_m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) input_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) clks[TEGRA20_CLK_CLK_M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* pll_ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) pll_ref_div = tegra20_get_pll_ref_div();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) CLK_SET_RATE_PARENT, 1, pll_ref_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) clks[TEGRA20_CLK_PLL_REF] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Tegra20 CPU clock and reset control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static void tegra20_wait_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) reg = readl(clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static void tegra20_put_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) writel(CPU_RESET(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static void tegra20_cpu_out_of_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) writel(CPU_RESET(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static void tegra20_enable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) writel(reg & ~CPU_CLOCK(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static void tegra20_disable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) writel(reg | CPU_CLOCK(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static bool tegra20_cpu_rail_off_ready(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned int cpu_rst_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) cpu_rst_status = readl(clk_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return !!(cpu_rst_status & 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static void tegra20_cpu_clock_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* switch coresite to clk_m, save off original source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) tegra20_cpu_clk_sctx.clk_csite_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) readl(clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) writel(3<<30, clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) tegra20_cpu_clk_sctx.cpu_burst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) readl(clk_base + CCLK_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) tegra20_cpu_clk_sctx.pllx_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) readl(clk_base + PLLX_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) tegra20_cpu_clk_sctx.pllx_misc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) readl(clk_base + PLLX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) tegra20_cpu_clk_sctx.cclk_divider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) readl(clk_base + SUPER_CCLK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void tegra20_cpu_clock_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned int reg, policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 misc, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Is CPU complex already running on PLLX? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) reg = readl(clk_base + CCLK_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (policy == CCLK_IDLE_POLICY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) else if (policy == CCLK_RUN_POLICY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (reg != CCLK_BURST_POLICY_PLLX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) misc = readl_relaxed(clk_base + PLLX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) base = readl_relaxed(clk_base + PLLX_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (misc != tegra20_cpu_clk_sctx.pllx_misc ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) base != tegra20_cpu_clk_sctx.pllx_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* restore PLLX settings if CPU is on different PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) writel(tegra20_cpu_clk_sctx.pllx_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) clk_base + PLLX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) writel(tegra20_cpu_clk_sctx.pllx_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) clk_base + PLLX_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* wait for PLL stabilization if PLLX was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * Restore original burst policy setting for calls resulting from CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * LP2 in idle or system suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) writel(tegra20_cpu_clk_sctx.cclk_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) clk_base + SUPER_CCLK_DIVIDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) writel(tegra20_cpu_clk_sctx.cpu_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) clk_base + CCLK_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) writel(tegra20_cpu_clk_sctx.clk_csite_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .wait_for_reset = tegra20_wait_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .put_in_reset = tegra20_put_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .out_of_reset = tegra20_cpu_out_of_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .enable_clock = tegra20_enable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .disable_clock = tegra20_disable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .rail_off_ready = tegra20_cpu_rail_off_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .suspend = tegra20_cpu_clock_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .resume = tegra20_cpu_clock_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static struct tegra_clk_init_table init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static void __init tegra20_clock_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Some clocks may be used by different drivers depending on the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * configuration. List those here to register them twice in the clock lookup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * table under two names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static const struct of_device_id pmc_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { .compatible = "nvidia,tegra20-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct clk_hw *parent_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) clk = of_clk_src_onecell_get(clkspec, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * clock is created by the pinctrl driver. It is possible for clk user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * to request these clocks before pinctrl driver got probed and hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * user will get an orphaned clock. That might be undesirable because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * user may expect parent clock to be enabled by the child.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) clkspec->args[0] == TEGRA20_CLK_CDEV2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) parent_hw = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!parent_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (clkspec->args[0] == TEGRA20_CLK_EMC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (!tegra20_clk_emc_driver_available(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static void __init tegra20_clock_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pr_err("Can't map CAR registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) node = of_find_matching_node(NULL, pmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) pr_err("Failed to find pmc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pmc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!pmc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pr_err("Can't map pmc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) TEGRA20_CLK_PERIPH_BANKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) tegra20_osc_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) tegra_fixed_clk_init(tegra20_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) tegra20_pll_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) tegra20_super_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) tegra20_periph_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) tegra20_audio_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) tegra_cpu_car_ops = &tegra20_cpu_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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