^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/tegra124-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/reset/tegra124-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * banks present in the Tegra124/132 CAR IP block. The banks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * identified by single letters, e.g.: L, H, U, V, W, X. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * periph_regs[] in drivers/clk/tegra/clk.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA124_CAR_BANK_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_SOURCE_CSITE 0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_SOURCE_EMC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_SOURCE_SOR0 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RST_DFLL_DVCO 0x2f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DVFS_DFLL_RESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLLC_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLC_OUT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLLC_MISC2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLLC_MISC 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLLC2_BASE 0x4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLLC2_MISC 0x4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLLC3_BASE 0x4fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLLC3_MISC 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLLM_BASE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLLM_OUT 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLLM_MISC 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLLP_BASE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLLP_MISC 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PLLA_BASE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLLA_MISC 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLLD_BASE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLLD_MISC 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLLU_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLLU_MISC 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLX_MISC 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLX_MISC2 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLLX_MISC3 0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLLE_BASE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLE_MISC 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLLD2_BASE 0x4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLLD2_MISC 0x4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLE_AUX 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLLRE_BASE 0x4c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLLRE_MISC 0x4c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLLDP_BASE 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLLDP_MISC 0x594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLLC4_BASE 0x5a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLLC4_MISC 0x5a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLC_IDDQ_BIT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLLRE_IDDQ_BIT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLLSS_IDDQ_BIT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLL_BASE_LOCK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLLE_MISC_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PLLRE_MISC_LOCK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PLL_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLLC_MISC_LOCK_ENABLE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PLLDU_MISC_LOCK_ENABLE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLLE_MISC_LOCK_ENABLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLLRE_MISC_LOCK_ENABLE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLLSS_MISC_LOCK_ENABLE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLLXC_SW_MAX_P 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PMC_PLLM_WB0_OVERRIDE 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CCLKG_BURST_POLICY 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Tegra CPU clock and reset control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MASK(x) (BIT(x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) _parents##_idx, 0, _lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NODIV(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) _mux_shift, _mux_mask, _clk_num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) _gate_flags, _clk_id, _lock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) _clk_id, _parents##_idx, 0, _lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct cpu_clk_suspend_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 clk_csite_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 cclkg_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 cclkg_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) } tegra124_cpu_clk_sctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static unsigned long osc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned long pll_ref_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static DEFINE_SPINLOCK(pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static DEFINE_SPINLOCK(pll_e_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static DEFINE_SPINLOCK(pll_re_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static DEFINE_SPINLOCK(pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static DEFINE_SPINLOCK(emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static DEFINE_SPINLOCK(sor0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* possible OSC frequencies in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static unsigned long tegra124_input_freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [ 0] = 13000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [ 1] = 16800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [ 4] = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [ 5] = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [ 8] = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [ 9] = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [12] = 26000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct div_nmp pllxc_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct pdiv_map pllxc_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .pdiv = 10, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .pdiv = 12, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .pdiv = 16, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .pdiv = 12, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .pdiv = 20, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .pdiv = 24, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .pdiv = 32, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct tegra_clk_pll_params pll_x_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .vco_min = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .vco_max = 3000000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .base_reg = PLLX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .misc_reg = PLLX_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .iddq_reg = PLLX_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .iddq_bit_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .max_p = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .dyn_ramp_reg = PLLX_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .stepa_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .stepb_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .pdiv_tohw = pllxc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .div_nmp = &pllxc_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .freq_table = pll_x_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 12000000, 624000000, 104, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 12000000, 600000000, 100, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct tegra_clk_pll_params pll_c_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .base_reg = PLLC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .misc_reg = PLLC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .iddq_reg = PLLC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .iddq_bit_idx = PLLC_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .max_p = PLLXC_SW_MAX_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .dyn_ramp_reg = PLLC_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .stepa_shift = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .stepb_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pdiv_tohw = pllxc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .div_nmp = &pllxc_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .freq_table = pll_c_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct div_nmp pllcx_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .divm_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct pdiv_map pllc_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .pdiv = 6, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .pdiv = 8, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .pdiv = 12, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .pdiv = 16, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 12000000, 600000000, 100, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct tegra_clk_pll_params pll_c2_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .input_max = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .base_reg = PLLC2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .misc_reg = PLLC2_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .pdiv_tohw = pllc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .div_nmp = &pllcx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .max_p = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .ext_misc_reg[0] = 0x4f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .ext_misc_reg[1] = 0x4f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .ext_misc_reg[2] = 0x4f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct tegra_clk_pll_params pll_c3_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .input_max = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .base_reg = PLLC3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .misc_reg = PLLC3_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .pdiv_tohw = pllc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .div_nmp = &pllcx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .max_p = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .ext_misc_reg[0] = 0x504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .ext_misc_reg[1] = 0x508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .ext_misc_reg[2] = 0x50c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct div_nmp pllss_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct pdiv_map pll12g_ssd_esd_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { .pdiv = 10, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { .pdiv = 12, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { .pdiv = 16, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { .pdiv = 12, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { .pdiv = 20, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { .pdiv = 24, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { .pdiv = 32, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 12000000, 600000000, 100, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct tegra_clk_pll_params pll_c4_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .base_reg = PLLC4_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .misc_reg = PLLC4_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .iddq_reg = PLLC4_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .iddq_bit_idx = PLLSS_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .pdiv_tohw = pll12g_ssd_esd_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .div_nmp = &pllss_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .ext_misc_reg[0] = 0x5ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .ext_misc_reg[1] = 0x5b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .ext_misc_reg[2] = 0x5b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .freq_table = pll_c4_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct pdiv_map pllm_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { .pdiv = 10, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .pdiv = 12, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { .pdiv = 16, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { .pdiv = 12, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { .pdiv = 20, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { .pdiv = 24, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { .pdiv = 32, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct div_nmp pllm_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .override_divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .override_divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .divp_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .override_divp_shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct tegra_clk_pll_params pll_m_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .input_max = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .vco_min = 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .vco_max = 1066000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .base_reg = PLLM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .misc_reg = PLLM_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .max_p = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .pdiv_tohw = pllm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .div_nmp = &pllm_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .freq_table = pll_m_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* PLLE special case: use cpcon field to store cml divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 336000000, 100000000, 100, 21, 16, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { 312000000, 100000000, 200, 26, 24, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { 13000000, 100000000, 200, 1, 26, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { 12000000, 100000000, 200, 1, 24, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct pdiv_map plle_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { .pdiv = 10, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { .pdiv = 12, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { .pdiv = 16, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { .pdiv = 12, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { .pdiv = 20, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { .pdiv = 24, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { .pdiv = 32, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct div_nmp plle_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .divp_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct tegra_clk_pll_params pll_e_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .cf_max = 75000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .vco_min = 1600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .vco_max = 2400000000U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .base_reg = PLLE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .misc_reg = PLLE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .aux_reg = PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .lock_mask = PLLE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .pdiv_tohw = plle_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .div_nmp = &plle_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .freq_table = pll_e_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .fixed_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct clk_div_table pll_re_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .val = 4, .div = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .val = 5, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { .val = 0, .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct div_nmp pllre_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .divp_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct tegra_clk_pll_params pll_re_vco_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .vco_min = 300000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .vco_max = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .base_reg = PLLRE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .misc_reg = PLLRE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .lock_mask = PLLRE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .iddq_reg = PLLRE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .iddq_bit_idx = PLLRE_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .div_nmp = &pllre_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) TEGRA_PLL_LOCK_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct div_nmp pllp_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .divm_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .divn_width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { 12000000, 408000000, 408, 12, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { 13000000, 408000000, 408, 13, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { 16800000, 408000000, 340, 14, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { 19200000, 408000000, 340, 16, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { 26000000, 408000000, 408, 26, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct tegra_clk_pll_params pll_p_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .vco_min = 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .base_reg = PLLP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .misc_reg = PLLP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .freq_table = pll_p_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .fixed_rate = 408000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { 9600000, 282240000, 147, 5, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { 9600000, 368640000, 192, 5, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { 9600000, 240000000, 200, 8, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 28800000, 282240000, 245, 25, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { 28800000, 368640000, 320, 25, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { 28800000, 240000000, 200, 24, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct tegra_clk_pll_params pll_a_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .vco_min = 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .base_reg = PLLA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .misc_reg = PLLA_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .freq_table = pll_a_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static struct div_nmp plld_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .divm_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .divn_width = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { 12000000, 216000000, 864, 12, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { 13000000, 216000000, 864, 13, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { 16800000, 216000000, 720, 14, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { 19200000, 216000000, 720, 16, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { 26000000, 216000000, 864, 26, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { 12000000, 594000000, 594, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { 13000000, 594000000, 594, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { 16800000, 594000000, 495, 14, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { 19200000, 594000000, 495, 16, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { 26000000, 594000000, 594, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { 12000000, 1000000000, 1000, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { 13000000, 1000000000, 1000, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { 19200000, 1000000000, 625, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { 26000000, 1000000000, 1000, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct tegra_clk_pll_params pll_d_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .vco_min = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .base_reg = PLLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .misc_reg = PLLD_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .div_nmp = &plld_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { 12000000, 594000000, 99, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static struct tegra_clk_pll_params tegra124_pll_d2_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .base_reg = PLLD2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .misc_reg = PLLD2_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .iddq_reg = PLLD2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .iddq_bit_idx = PLLSS_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .pdiv_tohw = pll12g_ssd_esd_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .div_nmp = &pllss_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .ext_misc_reg[0] = 0x570,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .ext_misc_reg[1] = 0x574,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .ext_misc_reg[2] = 0x578,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .max_p = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .freq_table = tegra124_pll_d2_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { 12000000, 600000000, 100, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct tegra_clk_pll_params pll_dp_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .base_reg = PLLDP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .misc_reg = PLLDP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .iddq_reg = PLLDP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .iddq_bit_idx = PLLSS_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .pdiv_tohw = pll12g_ssd_esd_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .div_nmp = &pllss_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .ext_misc_reg[0] = 0x598,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .ext_misc_reg[1] = 0x59c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .ext_misc_reg[2] = 0x5a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .max_p = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .freq_table = pll_dp_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct pdiv_map pllu_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { .pdiv = 1, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { .pdiv = 2, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static struct div_nmp pllu_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .divm_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .divn_width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .divp_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { 12000000, 480000000, 960, 12, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { 13000000, 480000000, 960, 13, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { 16800000, 480000000, 400, 7, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { 19200000, 480000000, 200, 4, 2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { 26000000, 480000000, 960, 26, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct tegra_clk_pll_params pll_u_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .vco_min = 480000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .vco_max = 960000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .base_reg = PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .misc_reg = PLLU_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .pdiv_tohw = pllu_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .div_nmp = &pllu_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .freq_table = pll_u_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static struct tegra_devclk devclks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const char * const sor0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "pll_d2_out0", "clk_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const char * const sor0_out_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "clk_m", "sor0_pad_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static struct tegra_periph_init_data tegra124_periph[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) CLK_SOURCE_SOR0, 29, 0x7, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 0, 182, 0, tegra_clk_sor0, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &sor0_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) NULL, 0, &sor0_lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static __init void tegra124_periph_clk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) void __iomem *pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* xusb_ss_div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) 1, 17, 181);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) clks[TEGRA124_CLK_DPAUX] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) clk_base, 0, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) clks[TEGRA124_CLK_DSIA] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) clk_base, 0, 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) clks[TEGRA124_CLK_DSIB] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) &emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clks[TEGRA124_CLK_MC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* cml0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) 0, 0, &pll_e_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) clk_register_clkdev(clk, "cml0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) clks[TEGRA124_CLK_CML0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* cml1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) 1, 0, &pll_e_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clk_register_clkdev(clk, "cml1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clks[TEGRA124_CLK_CML1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) for (i = 0; i < ARRAY_SIZE(tegra124_periph); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct tegra_periph_init_data *init = &tegra124_periph[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct clk **clkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) clkp = tegra_lookup_dt_id(init->clk_id, tegra124_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (!clkp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pr_warn("clock %u not found\n", init->clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) clk = tegra_clk_register_periph_data(clk_base, init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) *clkp = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static void __init tegra124_pll_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) void __iomem *pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* PLLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pmc, 0, &pll_c_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) clk_register_clkdev(clk, "pll_c", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) clks[TEGRA124_CLK_PLL_C] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* PLLC_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) clk_base + PLLC_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) clk_register_clkdev(clk, "pll_c_out1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* PLLC_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) clk_register_clkdev(clk, "pll_c_ud", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) clks[TEGRA124_CLK_PLL_C_UD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* PLLC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) &pll_c2_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) clk_register_clkdev(clk, "pll_c2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) clks[TEGRA124_CLK_PLL_C2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* PLLC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) &pll_c3_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) clk_register_clkdev(clk, "pll_c3", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) clks[TEGRA124_CLK_PLL_C3] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* PLLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) CLK_SET_RATE_GATE, &pll_m_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) clk_register_clkdev(clk, "pll_m", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) clks[TEGRA124_CLK_PLL_M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* PLLM_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) clk_base + PLLM_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) clk_register_clkdev(clk, "pll_m_out1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* PLLM_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) clk_register_clkdev(clk, "pll_m_ud", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) clks[TEGRA124_CLK_PLL_M_UD] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* PLLU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) &pll_u_params, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) clk_register_clkdev(clk, "pll_u", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) clks[TEGRA124_CLK_PLL_U] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* PLLU_480M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) 22, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) clk_register_clkdev(clk, "pll_u_480M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) clks[TEGRA124_CLK_PLL_U_480M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* PLLU_60M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) CLK_SET_RATE_PARENT, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) clk_register_clkdev(clk, "pll_u_60M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) clks[TEGRA124_CLK_PLL_U_60M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* PLLU_48M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) CLK_SET_RATE_PARENT, 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) clk_register_clkdev(clk, "pll_u_48M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) clks[TEGRA124_CLK_PLL_U_48M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* PLLU_12M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) CLK_SET_RATE_PARENT, 1, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) clk_register_clkdev(clk, "pll_u_12M", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) clks[TEGRA124_CLK_PLL_U_12M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* PLLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) &pll_d_params, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) clk_register_clkdev(clk, "pll_d", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) clks[TEGRA124_CLK_PLL_D] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* PLLD_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) clk_register_clkdev(clk, "pll_d_out0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* PLLRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) clk_register_clkdev(clk, "pll_re_vco", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) clk_base + PLLRE_BASE, 16, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pll_re_div_table, &pll_re_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) clk_register_clkdev(clk, "pll_re_out", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* PLLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) clk_base, 0, &pll_e_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) clk_register_clkdev(clk, "pll_e", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) clks[TEGRA124_CLK_PLL_E] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* PLLC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) &pll_c4_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) clk_register_clkdev(clk, "pll_c4", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) clks[TEGRA124_CLK_PLL_C4] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* PLLDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) &pll_dp_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) clk_register_clkdev(clk, "pll_dp", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) clks[TEGRA124_CLK_PLL_DP] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* PLLD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) &tegra124_pll_d2_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) clk_register_clkdev(clk, "pll_d2", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) clks[TEGRA124_CLK_PLL_D2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* PLLD2_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) clk_register_clkdev(clk, "pll_d2_out0", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Tegra124 CPU clock and reset control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static void tegra124_wait_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static void tegra124_disable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* flow controller would take care in the power sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static void tegra124_cpu_clock_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* switch coresite to clk_m, save off original source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) tegra124_cpu_clk_sctx.clk_csite_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) readl(clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) tegra124_cpu_clk_sctx.cclkg_burst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) readl(clk_base + CCLKG_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) tegra124_cpu_clk_sctx.cclkg_divider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) readl(clk_base + CCLKG_BURST_POLICY + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static void tegra124_cpu_clock_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) writel(tegra124_cpu_clk_sctx.clk_csite_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) writel(tegra124_cpu_clk_sctx.cclkg_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) clk_base + CCLKG_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) writel(tegra124_cpu_clk_sctx.cclkg_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) clk_base + CCLKG_BURST_POLICY + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .wait_for_reset = tegra124_wait_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .disable_clock = tegra124_disable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .suspend = tegra124_cpu_clock_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .resume = tegra124_cpu_clock_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct of_device_id pmc_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { .compatible = "nvidia,tegra124-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static struct tegra_clk_init_table common_init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 282240000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) { TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) { TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* Tegra132 requires the SOC_THERM clock to remain active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static struct tegra_audio_clk_info tegra124_audio_plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * Program an initial clock rate and enable or disable clocks needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * by the rest of the kernel, for Tegra124 SoCs. It is intended to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * called by assigning a pointer to it to tegra_clk_apply_init_table -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * this will be called as an arch_initcall. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static void __init tegra124_clock_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * tegra124_car_barrier - wait for pending writes to the CAR to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * Wait for any outstanding writes to the CAR MMIO space from this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * to complete before continuing execution. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static void tegra124_car_barrier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * Assert the reset line of the DFLL's DVCO. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static void tegra124_clock_assert_dfll_dvco_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) v = readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) v |= (1 << DVFS_DFLL_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) writel_relaxed(v, clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) tegra124_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * operate. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static void tegra124_clock_deassert_dfll_dvco_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) v = readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) writel_relaxed(v, clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) tegra124_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static int tegra124_reset_assert(unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (id == TEGRA124_RST_DFLL_DVCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) tegra124_clock_assert_dfll_dvco_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int tegra124_reset_deassert(unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (id == TEGRA124_RST_DFLL_DVCO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) tegra124_clock_deassert_dfll_dvco_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * Program an initial clock rate and enable or disable clocks needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * by the rest of the kernel, for Tegra132 SoCs. It is intended to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * called by assigning a pointer to it to tegra_clk_apply_init_table -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * this will be called as an arch_initcall. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static void __init tegra132_clock_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * @np: struct device_node * of the DT node for the SoC CAR IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Register most of the clocks controlled by the CAR IP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * Everything in this function should be common to Tegra124 and Tegra132.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static void __init tegra124_132_clock_init_pre(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) u32 plld_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pr_err("ioremap tegra124/tegra132 CAR failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) node = of_find_matching_node(NULL, pmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) pr_err("Failed to find pmc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) pmc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (!pmc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) pr_err("Can't map pmc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) TEGRA124_CAR_BANK_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) &pll_ref_freq) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) tegra_fixed_clk_init(tegra124_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) tegra124_pll_init(clk_base, pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) tegra124_periph_clk_init(clk_base, pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) tegra124_audio_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ARRAY_SIZE(tegra124_audio_plls), 24576000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) plld_base = readl(clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) plld_base &= ~BIT(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) writel(plld_base, clk_base + PLLD_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * @np: struct device_node * of the DT node for the SoC CAR IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * Register most of the clocks controlled by the CAR IP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * Everything in this function should be common to Tegra124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * and Tegra132. This function must be called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static void __init tegra124_132_clock_init_post(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) &pll_x_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) tegra_init_special_resets(1, tegra124_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) tegra124_reset_deassert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) tegra_add_of_provider(np, of_clk_src_onecell_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) &emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) tegra_cpu_car_ops = &tegra124_cpu_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * tegra124_clock_init - Tegra124-specific clock initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * @np: struct device_node * of the DT node for the SoC CAR IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * Register most SoC clocks for the Tegra124 system-on-chip. Most of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * this code is shared between the Tegra124 and Tegra132 SoCs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * although some of the initial clock settings and CPU clocks differ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * Intended to be called by the OF init code when a DT node with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * "nvidia,tegra124-car" string is encountered, and declared with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * CLK_OF_DECLARE. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static void __init tegra124_clock_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) tegra124_132_clock_init_pre(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) tegra124_132_clock_init_post(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * tegra132_clock_init - Tegra132-specific clock initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * @np: struct device_node * of the DT node for the SoC CAR IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * Register most SoC clocks for the Tegra132 system-on-chip. Most of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * this code is shared between the Tegra124 and Tegra132 SoCs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * although some of the initial clock settings and CPU clocks differ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * Intended to be called by the OF init code when a DT node with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * "nvidia,tegra132-car" string is encountered, and declared with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * CLK_OF_DECLARE. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static void __init tegra132_clock_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) tegra124_132_clock_init_pre(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * On Tegra132, these clocks are controlled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * CLUSTER_clocks IP block, located in the CPU complex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) tegra124_clks[tegra_clk_cclk_g].present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) tegra124_clks[tegra_clk_cclk_lp].present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) tegra124_clks[tegra_clk_pll_x].present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) tegra124_clks[tegra_clk_pll_x_out0].present = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) tegra124_132_clock_init_post(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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