^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/tegra114-car.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RST_DFLL_DVCO 0x2F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* RST_DFLL_DVCO bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DVFS_DFLL_RESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* CPU_FINETRIM_R bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA114_CLK_PERIPH_BANKS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLLC_BASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLLC_MISC2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLLC_MISC 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLLC2_BASE 0x4e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLLC2_MISC 0x4ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLC3_BASE 0x4fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLC3_MISC 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLLM_BASE 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLLM_MISC 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLP_BASE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLLP_MISC 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLX_MISC 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLLX_MISC2 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLLX_MISC3 0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLLD_BASE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLLD_MISC 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLLD2_BASE 0x4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLLD2_MISC 0x4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLLE_BASE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLE_MISC 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLLA_BASE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLLA_MISC 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLLU_BASE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLLU_MISC 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLLRE_BASE 0x4c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PLLRE_MISC 0x4c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PLL_MISC_LOCK_ENABLE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLLC_MISC_LOCK_ENABLE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PLLDU_MISC_LOCK_ENABLE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLLE_MISC_LOCK_ENABLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLLRE_MISC_LOCK_ENABLE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLLC_IDDQ_BIT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLLX_IDDQ_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PLLRE_IDDQ_BIT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PLL_BASE_LOCK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PLLE_MISC_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLLRE_MISC_LOCK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PLLE_AUX 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PLLC_OUT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PLLM_OUT 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OSC_CTRL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OSC_CTRL_OSC_FREQ_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLLXC_SW_MAX_P 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CCLKG_BURST_POLICY 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_SOURCE_CSITE 0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_SOURCE_EMC 0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* PLLM override registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMC_PLLM_WB0_OVERRIDE 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Tegra CPU clock and reset control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MUX8(_name, _parents, _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) _clk_num, _gate_flags, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct cpu_clk_suspend_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 clk_csite_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 cclkg_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 cclkg_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } tegra114_cpu_clk_sctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static DEFINE_SPINLOCK(pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static DEFINE_SPINLOCK(pll_d2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static DEFINE_SPINLOCK(pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static DEFINE_SPINLOCK(pll_re_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static DEFINE_SPINLOCK(emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct div_nmp pllxc_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct pdiv_map pllxc_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .pdiv = 10, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .pdiv = 12, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { .pdiv = 16, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .pdiv = 12, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .pdiv = 20, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .pdiv = 24, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .pdiv = 32, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 12000000, 624000000, 104, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 12000000, 600000000, 100, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct tegra_clk_pll_params pll_c_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .vco_max = 1400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .base_reg = PLLC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .misc_reg = PLLC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .iddq_reg = PLLC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .iddq_bit_idx = PLLC_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .max_p = PLLXC_SW_MAX_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .dyn_ramp_reg = PLLC_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .stepa_shift = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .stepb_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .pdiv_tohw = pllxc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .div_nmp = &pllxc_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .freq_table = pll_c_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct div_nmp pllcx_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .divm_width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct pdiv_map pllc_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .pdiv = 8, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .pdiv = 16, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 12000000, 600000000, 100, 1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct tegra_clk_pll_params pll_c2_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .input_max = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .base_reg = PLLC2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .misc_reg = PLLC2_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .pdiv_tohw = pllc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .div_nmp = &pllcx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .max_p = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ext_misc_reg[0] = 0x4f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .ext_misc_reg[1] = 0x4f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .ext_misc_reg[2] = 0x4f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct tegra_clk_pll_params pll_c3_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .input_max = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .cf_max = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .vco_min = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .vco_max = 1200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .base_reg = PLLC3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .misc_reg = PLLC3_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .pdiv_tohw = pllc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .div_nmp = &pllcx_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .max_p = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .ext_misc_reg[0] = 0x504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .ext_misc_reg[1] = 0x508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .ext_misc_reg[2] = 0x50c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .freq_table = pll_cx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .flags = TEGRA_PLL_USE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct div_nmp pllm_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .override_divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .override_divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .divp_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .override_divp_shift = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct pdiv_map pllm_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct tegra_clk_pll_params pll_m_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .input_max = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .vco_min = 400000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .vco_max = 1066000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .base_reg = PLLM_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .misc_reg = PLLM_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .max_p = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .pdiv_tohw = pllm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .div_nmp = &pllm_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .freq_table = pll_m_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) TEGRA_PLL_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct div_nmp pllp_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .divm_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .divn_width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .divp_width = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 12000000, 216000000, 432, 12, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 13000000, 216000000, 432, 13, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 16800000, 216000000, 360, 14, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 19200000, 216000000, 360, 16, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 26000000, 216000000, 432, 26, 2, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct tegra_clk_pll_params pll_p_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .vco_min = 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .base_reg = PLLP_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .misc_reg = PLLP_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .freq_table = pll_p_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .fixed_rate = 408000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 9600000, 282240000, 147, 5, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { 9600000, 368640000, 192, 5, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { 9600000, 240000000, 200, 8, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { 28800000, 282240000, 245, 25, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { 28800000, 368640000, 320, 25, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { 28800000, 240000000, 200, 24, 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct tegra_clk_pll_params pll_a_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .input_max = 31000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .vco_min = 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .vco_max = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .base_reg = PLLA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .misc_reg = PLLA_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .freq_table = pll_a_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 12000000, 216000000, 864, 12, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 13000000, 216000000, 864, 13, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 16800000, 216000000, 720, 14, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 19200000, 216000000, 720, 16, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 26000000, 216000000, 864, 26, 4, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 12000000, 594000000, 594, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 13000000, 594000000, 594, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 16800000, 594000000, 495, 14, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 19200000, 594000000, 495, 16, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 26000000, 594000000, 594, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 12000000, 1000000000, 1000, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 13000000, 1000000000, 1000, 13, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 19200000, 1000000000, 625, 12, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 26000000, 1000000000, 1000, 26, 1, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct tegra_clk_pll_params pll_d_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .vco_min = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .base_reg = PLLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .misc_reg = PLLD_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct tegra_clk_pll_params pll_d2_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .vco_min = 500000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .vco_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .base_reg = PLLD2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .misc_reg = PLLD2_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .div_nmp = &pllp_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .freq_table = pll_d_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct pdiv_map pllu_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { .pdiv = 1, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { .pdiv = 2, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { .pdiv = 0, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct div_nmp pllu_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .divm_width = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .divn_width = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .divp_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .divp_width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 12000000, 480000000, 960, 12, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { 13000000, 480000000, 960, 13, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 16800000, 480000000, 400, 7, 2, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { 19200000, 480000000, 200, 4, 2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { 26000000, 480000000, 960, 26, 2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct tegra_clk_pll_params pll_u_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .input_min = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .input_max = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .cf_min = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .cf_max = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .vco_min = 480000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .vco_max = 960000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .base_reg = PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .misc_reg = PLLU_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .lock_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .pdiv_tohw = pllu_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .div_nmp = &pllu_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .freq_table = pll_u_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* 1 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct tegra_clk_pll_params pll_x_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .input_max = 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .vco_min = 700000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .vco_max = 2400000000U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .base_reg = PLLX_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .misc_reg = PLLX_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .lock_mask = PLL_BASE_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .iddq_reg = PLLX_MISC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .iddq_bit_idx = PLLX_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .max_p = PLLXC_SW_MAX_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .dyn_ramp_reg = PLLX_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .stepa_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .stepb_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .pdiv_tohw = pllxc_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .div_nmp = &pllxc_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .freq_table = pll_x_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* PLLE special case: use cpcon field to store cml divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { 336000000, 100000000, 100, 21, 16, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { 312000000, 100000000, 200, 26, 24, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { 12000000, 100000000, 200, 1, 24, 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct pdiv_map plle_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { .pdiv = 1, .hw_val = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { .pdiv = 2, .hw_val = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { .pdiv = 3, .hw_val = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { .pdiv = 4, .hw_val = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { .pdiv = 5, .hw_val = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { .pdiv = 6, .hw_val = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { .pdiv = 8, .hw_val = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { .pdiv = 10, .hw_val = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { .pdiv = 12, .hw_val = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .pdiv = 16, .hw_val = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .pdiv = 12, .hw_val = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .pdiv = 16, .hw_val = 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .pdiv = 20, .hw_val = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .pdiv = 24, .hw_val = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .pdiv = 32, .hw_val = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .pdiv = 0, .hw_val = 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct div_nmp plle_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .divp_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static struct tegra_clk_pll_params pll_e_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .cf_max = 75000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .vco_min = 1600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .vco_max = 2400000000U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .base_reg = PLLE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .misc_reg = PLLE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .aux_reg = PLLE_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .lock_mask = PLLE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .pdiv_tohw = plle_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .div_nmp = &plle_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .freq_table = pll_e_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .fixed_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct div_nmp pllre_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .divm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .divm_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .divn_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .divn_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .divp_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .divp_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static struct tegra_clk_pll_params pll_re_vco_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .input_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .input_max = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .cf_min = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .vco_min = 300000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .vco_max = 600000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .base_reg = PLLRE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .misc_reg = PLLRE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .lock_mask = PLLRE_MISC_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .lock_delay = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .iddq_reg = PLLRE_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .iddq_bit_idx = PLLRE_IDDQ_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .div_nmp = &pllre_nmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) TEGRA_PLL_LOCK_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* possible OSC frequencies in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static unsigned long tegra114_input_freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) [ 0] = 13000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) [ 1] = 16800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) [ 4] = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) [ 5] = 38400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) [ 8] = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [ 9] = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [12] = 26000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define MASK(x) (BIT(x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* peripheral mux definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const char *mux_plld_out0_plld2_out0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "pll_d_out0", "pll_d2_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define mux_plld_out0_plld2_out0_idx NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const char *mux_pllmcp_clkm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct clk_div_table pll_re_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .val = 4, .div = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .val = 5, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .val = 0, .div = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct tegra_devclk devclks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static struct tegra_audio_clk_info tegra114_audio_plls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static unsigned long osc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static unsigned long pll_ref_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* clk_32k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) clks[TEGRA114_CLK_CLK_32K] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static void __init tegra114_pll_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) void __iomem *pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* PLLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pmc, 0, &pll_c_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clks[TEGRA114_CLK_PLL_C] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* PLLC_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) clk_base + PLLC_OUT, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* PLLC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &pll_c2_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) clks[TEGRA114_CLK_PLL_C2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* PLLC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &pll_c3_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clks[TEGRA114_CLK_PLL_C3] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* PLLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) CLK_SET_RATE_GATE, &pll_m_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) clks[TEGRA114_CLK_PLL_M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* PLLM_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) 8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* PLLM_UD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) CLK_SET_RATE_PARENT, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* PLLU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &pll_u_params, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) clks[TEGRA114_CLK_PLL_U] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* PLLU_480M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) 22, 0, &pll_u_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) clks[TEGRA114_CLK_PLL_U_480M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* PLLU_60M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) CLK_SET_RATE_PARENT, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) clks[TEGRA114_CLK_PLL_U_60M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* PLLU_48M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) CLK_SET_RATE_PARENT, 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) clks[TEGRA114_CLK_PLL_U_48M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* PLLU_12M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) CLK_SET_RATE_PARENT, 1, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) clks[TEGRA114_CLK_PLL_U_12M] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* PLLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) &pll_d_params, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) clks[TEGRA114_CLK_PLL_D] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* PLLD_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* PLLD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) &pll_d2_params, &pll_d2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) clks[TEGRA114_CLK_PLL_D2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* PLLD2_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* PLLRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) clk_base + PLLRE_BASE, 16, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pll_re_div_table, &pll_re_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* PLLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) clk_base, 0, &pll_e_params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define CLK_SOURCE_VI_SENSOR 0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static struct tegra_periph_init_data tegra_periph_clk_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static __init void tegra114_periph_clk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) void __iomem *pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct tegra_periph_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* xusb_ss_div2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* dsia mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ARRAY_SIZE(mux_plld_out0_plld2_out0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) clks[TEGRA114_CLK_DSIA_MUX] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* dsib mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ARRAY_SIZE(mux_plld_out0_plld2_out0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) clks[TEGRA114_CLK_DSIB_MUX] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) 0, 48, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) clks[TEGRA114_CLK_DSIA] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) 0, 82, periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) clks[TEGRA114_CLK_DSIB] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* emc mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ARRAY_SIZE(mux_pllmcp_clkm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) clk_base + CLK_SOURCE_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) 29, 3, 0, &emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) &emc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) clks[TEGRA114_CLK_MC] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) CLK_SET_RATE_PARENT, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) clks[TEGRA114_CLK_MIPI_CAL] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) data = &tegra_periph_clk_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clk = tegra_clk_register_periph_data(clk_base, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clks[data->clk_id] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) &pll_p_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Tegra114 CPU clock and reset control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static void tegra114_wait_cpu_in_reset(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static void tegra114_disable_cpu_clock(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* flow controller would take care in the power sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void tegra114_cpu_clock_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* switch coresite to clk_m, save off original source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) tegra114_cpu_clk_sctx.clk_csite_src =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) readl(clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) tegra114_cpu_clk_sctx.cclkg_burst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) readl(clk_base + CCLKG_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) tegra114_cpu_clk_sctx.cclkg_divider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) readl(clk_base + CCLKG_BURST_POLICY + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void tegra114_cpu_clock_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) writel(tegra114_cpu_clk_sctx.clk_csite_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) clk_base + CLK_SOURCE_CSITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) writel(tegra114_cpu_clk_sctx.cclkg_burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) clk_base + CCLKG_BURST_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) writel(tegra114_cpu_clk_sctx.cclkg_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) clk_base + CCLKG_BURST_POLICY + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .wait_for_reset = tegra114_wait_cpu_in_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .disable_clock = tegra114_disable_cpu_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .suspend = tegra114_cpu_clock_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .resume = tegra114_cpu_clock_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct of_device_id pmc_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) { .compatible = "nvidia,tegra114-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * breaks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static struct tegra_clk_init_table init_table[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) { TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* must be the last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static void __init tegra114_clock_apply_init_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * tegra114_car_barrier - wait for pending writes to the CAR to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * Wait for any outstanding writes to the CAR MMIO space from this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * to complete before continuing execution. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static void tegra114_car_barrier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) wmb(); /* probably unnecessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * When the CPU rail voltage is in the high-voltage range, use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * built-in hardwired clock propagation delays in the CPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * shaper. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) void tegra114_clock_tune_cpu_trimmers_high(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u32 select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Use hardwired rise->rise & fall->fall clock propagation delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) tegra114_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * When the CPU rail voltage is in the low-voltage range, use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * extended clock propagation delays set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * tegra114_clock_tune_cpu_trimmers_init(). The intention is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * maintain the input clock duty cycle that the FCPU subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * expects. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) void tegra114_clock_tune_cpu_trimmers_low(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u32 select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Use software-specified rise->rise & fall->fall clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * propagation delays (from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * tegra114_clock_tune_cpu_trimmers_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) tegra114_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * Program extended clock propagation delays into the FCPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * shaper and enable them. XXX Define the purpose - peak current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * reduction? No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* XXX Initial voltage rail state assumption issues? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) void tegra114_clock_tune_cpu_trimmers_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) u32 dr = 0, r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Increment the rise->rise clock delay by four steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) writel_relaxed(r, clk_base + CPU_FINETRIM_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * Use the rise->rise clock propagation delay specified in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * r field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) tegra114_clock_tune_cpu_trimmers_low();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * Assert the reset line of the DFLL's DVCO. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) void tegra114_clock_assert_dfll_dvco_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) v = readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) v |= (1 << DVFS_DFLL_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) writel_relaxed(v, clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tegra114_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * operate. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) void tegra114_clock_deassert_dfll_dvco_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) v = readl_relaxed(clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) writel_relaxed(v, clk_base + RST_DFLL_DVCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) tegra114_car_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static void __init tegra114_clock_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) pr_err("ioremap tegra114 CAR failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) node = of_find_matching_node(NULL, pmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) pr_err("Failed to find pmc node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pmc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!pmc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) pr_err("Can't map pmc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) TEGRA114_CLK_PERIPH_BANKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &pll_ref_freq) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) tegra114_fixed_clk_init(clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) tegra114_pll_init(clk_base, pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) tegra114_periph_clk_init(clk_base, pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) tegra114_audio_plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ARRAY_SIZE(tegra114_audio_plls), 24000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &pll_x_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) tegra_add_of_provider(np, of_clk_src_onecell_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) tegra_cpu_car_ops = &tegra114_cpu_car_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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