Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PLLX_BASE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PLLX_MISC 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PLLX_MISC2 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PLLX_MISC3 0x518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CCLKG_BURST_POLICY 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CCLKLP_BURST_POLICY 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_BURST_POLICY 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SYSTEM_CLK_RATE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_DIVIDER 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static DEFINE_SPINLOCK(sysrate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) enum tegra_super_gen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	gen4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	gen5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct tegra_super_gen_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	enum tegra_super_gen gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	const char **sclk_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	const char **cclk_g_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	const char **cclk_lp_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int num_sclk_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int num_cclk_g_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int num_cclk_lp_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			       "pll_p", "pll_p_out2", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			       "clk_32k", "pll_m_out1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 					"pll_p", "pll_p_out4", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					"unused", "pll_x", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 					"unused", "unused", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					"dfllCPU_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 					 "pll_p", "pll_p_out4", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					 "unused", "pll_x", "pll_x_out0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.gen = gen4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.sclk_parents = sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.cclk_g_parents = cclk_g_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.cclk_lp_parents = cclk_lp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.num_sclk_parents = ARRAY_SIZE(sclk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			       "pll_p", "pll_p_out2", "pll_c4_out1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			       "clk_32k", "pll_c4_out2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					"pll_p", "pll_p_out4", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 					"unused", "pll_x", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					"unused", "unused", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					"dfllCPU_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 					"pll_p", "pll_p_out4", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 					"unused", "pll_x", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					"unused", "unused", "unused", "unused",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					"dfllCPU_out" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.gen = gen5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.sclk_parents = sclk_parents_gen5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.cclk_g_parents = cclk_g_parents_gen5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.cclk_lp_parents = cclk_lp_parents_gen5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void __init tegra_sclk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				const struct tegra_super_gen_info *gen_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct clk **dt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* SCLK_MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		clk = tegra_clk_register_super_mux("sclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						gen_info->sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 						gen_info->num_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 						CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 						clk_base + SCLK_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 						0, 4, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		/* SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			clk = clk_register_divider(NULL, "sclk", "sclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 						CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 						clk_base + SCLK_DIVIDER, 0, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 						0, &sysrate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			clk = tegra_clk_register_super_mux("sclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 						gen_info->sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 						gen_info->num_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 						CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 						CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 						clk_base + SCLK_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 						0, 4, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* HCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				   clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				   &sysrate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		clk = clk_register_gate(NULL, "hclk", "hclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				clk_base + SYSTEM_CLK_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* PCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				   clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				   &sysrate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void __init tegra_super_clk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				void __iomem *pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				struct tegra_clk_pll_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				const struct tegra_super_gen_info *gen_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct clk **dt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* CCLKG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		if (gen_info->gen == gen5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			clk = tegra_clk_register_super_mux("cclk_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					gen_info->cclk_g_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					gen_info->num_cclk_g_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 					clk_base + CCLKG_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					TEGRA210_CPU_CLK, 4, 8, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			clk = tegra_clk_register_super_mux("cclk_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					gen_info->cclk_g_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 					gen_info->num_cclk_g_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 					clk_base + CCLKG_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					0, 4, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* CCLKLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (gen_info->gen == gen5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			 * TEGRA210_CPU_CLK flag is not needed for cclk_lp as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			 * cluster switching is not currently supported on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			 * Tegra210 and also cpu_lp is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			clk = tegra_clk_register_super_mux("cclk_lp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					gen_info->cclk_lp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					gen_info->num_cclk_lp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					clk_base + CCLKLP_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 					0, 4, 8, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			clk = tegra_clk_register_super_mux("cclk_lp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					gen_info->cclk_lp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 					gen_info->num_cclk_lp_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 					CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 					clk_base + CCLKLP_BURST_POLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 					TEGRA_DIVIDER_2, 4, 8, 9, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	tegra_sclk_init(clk_base, tegra_clks, gen_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)     defined(CONFIG_ARCH_TEGRA_124_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)     defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* PLLX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #if defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (gen_info->gen == gen5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		clk = tegra_clk_register_pllc_tegra210("pll_x", "pll_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			clk_base, pmc_base, CLK_IGNORE_UNUSED, params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				pmc_base, CLK_IGNORE_UNUSED, params, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* PLLX_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					CLK_SET_RATE_PARENT, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				void __iomem *pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				struct tegra_clk_pll_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			     &tegra_super_gen_info_gen4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void __init tegra_super_clk_gen5_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				void __iomem *pmc_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				struct tegra_clk_pll_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			     &tegra_super_gen_info_gen5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }