Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AUDIO_SYNC_CLK_I2S0 0x4a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AUDIO_SYNC_CLK_I2S1 0x4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AUDIO_SYNC_CLK_I2S2 0x4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AUDIO_SYNC_CLK_I2S3 0x4ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AUDIO_SYNC_CLK_I2S4 0x4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AUDIO_SYNC_CLK_SPDIF 0x4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AUDIO_SYNC_CLK_DMIC1 0x560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AUDIO_SYNC_CLK_DMIC2 0x564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AUDIO_SYNC_CLK_DMIC3 0x6b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AUDIO_SYNC_DOUBLER 0x49c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PLLA_OUT 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct tegra_sync_source_initdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned long	rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long	max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int		clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SYNC(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.name		= #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.clk_id		= tegra_clk_ ## _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct tegra_audio_clk_initdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	char		*gate_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	char		*mux_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32		offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int		gate_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int		mux_clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AUDIO(_name, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.gate_name	= #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.mux_name	= #_name"_mux",\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.offset		= _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.gate_clk_id	= tegra_clk_ ## _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.mux_clk_id	= tegra_clk_ ## _name ## _mux,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct tegra_audio2x_clk_initdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	char		*parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	char		*gate_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	char		*name_2x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	char		*div_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int		clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int		clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8		div_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AUDIO2X(_name, _num, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.parent		= #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.gate_name	= #_name"_2x",\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.name_2x	= #_name"_doubler",\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.div_name	= #_name"_div",\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.clk_id		= tegra_clk_ ## _name ## _2x,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.clk_num	= _num,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.div_offset	= _offset,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static DEFINE_SPINLOCK(clk_doubler_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static const char * const mux_audio_sync_clk[] = { "spdif_in_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	"i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	"pll_a_out0", "vimclk_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	"i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	"vimclk_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	SYNC(spdif_in_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	SYNC(i2s0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	SYNC(i2s1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	SYNC(i2s2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	SYNC(i2s3_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	SYNC(i2s4_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	SYNC(vimclk_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct tegra_audio_clk_initdata audio_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct tegra_audio_clk_initdata dmic_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	AUDIO2X(audio0, 113, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	AUDIO2X(audio1, 114, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	AUDIO2X(audio2, 115, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	AUDIO2X(audio3, 116, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	AUDIO2X(audio4, 117, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	AUDIO2X(spdif, 118, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				      struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				      struct tegra_audio_clk_initdata *sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				      int num_sync_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				      const char * const *mux_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				      int num_mux_inputs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct clk **dt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct tegra_audio_clk_initdata *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		clk = clk_register_mux(NULL, data->mux_name, mux_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					num_mux_inputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 					clk_base + data->offset, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 					NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					0, clk_base + data->offset, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					CLK_GATE_SET_TO_DISABLE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void __init tegra_audio_clk_init(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			void __iomem *pmc_base, struct tegra_clk *tegra_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			struct tegra_audio_clk_info *audio_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			unsigned int num_plls, unsigned long sync_max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct clk **dt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!audio_info || num_plls < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		pr_err("No audio data passed to tegra_audio_clk_init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (i = 0; i < num_plls; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		struct tegra_audio_clk_info *info = &audio_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			clk = tegra_clk_register_pll(info->name, info->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					clk_base, pmc_base, 0, info->pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* PLLA_OUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (dt_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				8, 8, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				CLK_SET_RATE_PARENT, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		struct tegra_sync_source_initdata *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		data = &sync_source_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		clk = tegra_clk_register_sync_source(data->name, sync_max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				  ARRAY_SIZE(audio_clks), mux_audio_sync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				  ARRAY_SIZE(mux_audio_sync_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* make sure the DMIC sync clocks have a valid parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	for (i = 0; i < ARRAY_SIZE(dmic_clks); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		writel_relaxed(1, clk_base + dmic_clks[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				  ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				  ARRAY_SIZE(mux_dmic_sync_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		struct tegra_audio2x_clk_initdata *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		data = &audio2x_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (!dt_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		clk = clk_register_fixed_factor(NULL, data->name_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				data->parent, CLK_SET_RATE_PARENT, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		clk = tegra_clk_register_divider(data->div_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				0, 0, data->div_offset, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				&clk_doubler_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		clk = tegra_clk_register_periph_gate(data->gate_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				data->div_name, TEGRA_PERIPH_NO_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				clk_base, CLK_SET_RATE_PARENT, data->clk_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				periph_clk_enb_refcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		*dt_clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)