^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SUPER_STATE_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SUPER_STATE_RUN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SUPER_STATE_IRQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SUPER_STATE_FIQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SUPER_STATE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) << SUPER_STATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUPER_LP_DIV2_BYPASS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define super_state_to_src_shift(m, s) ((m->width * s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define super_state_to_src_mask(m) (((1 << m->width) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCLK_SRC_PLLP_OUT0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCLK_SRC_PLLP_OUT4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static u8 clk_super_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 val, state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 source, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) val = readl_relaxed(mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) state = val & SUPER_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (state != super_state(SUPER_STATE_IDLE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) shift = (state == super_state(SUPER_STATE_IDLE)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) super_state_to_src_shift(mux, SUPER_STATE_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) source = (val >> shift) & super_state_to_src_mask(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * If LP_DIV2_BYPASS is not set and PLLX is current parent then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * PLLX/2 is the input source to CCLKLP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (source == mux->pllx_index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) source = mux->div2_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int clk_super_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 val, state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 parent_index, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) spin_lock_irqsave(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val = readl_relaxed(mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) state = val & SUPER_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (state != super_state(SUPER_STATE_IDLE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) shift = (state == super_state(SUPER_STATE_IDLE)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) super_state_to_src_shift(mux, SUPER_STATE_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * For LP mode super-clock switch between PLLX direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * and divided-by-2 outputs is allowed only when other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * than PLLX clock source is current parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (index == mux->pllx_index))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) parent_index = clk_super_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if ((parent_index == mux->div2_index) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (parent_index == mux->pllx_index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val ^= SUPER_LP_DIV2_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel_relaxed(val, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (index == mux->div2_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) index = mux->pllx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* enable PLLP branches to CPU before selecting PLLP source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if ((mux->flags & TEGRA210_CPU_CLK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (index == CCLK_SRC_PLLP_OUT0 || index == CCLK_SRC_PLLP_OUT4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tegra_clk_set_pllp_out_cpu(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val &= ~((super_state_to_src_mask(mux)) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= (index & (super_state_to_src_mask(mux))) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel_relaxed(val, mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* disable PLLP branches to CPU if not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if ((mux->flags & TEGRA210_CPU_CLK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tegra_clk_set_pllp_out_cpu(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_unlock_irqrestore(mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void clk_super_mux_restore_context(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int parent_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) parent_id = clk_hw_get_parent_index(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (WARN_ON(parent_id < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_super_set_parent(hw, parent_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct clk_ops tegra_clk_super_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .get_parent = clk_super_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .set_parent = clk_super_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .restore_context = clk_super_mux_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk_hw *div_hw = &super->frac_div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __clk_hw_set_clk(div_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return super->div_ops->round_rate(div_hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct clk_hw *div_hw = &super->frac_div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __clk_hw_set_clk(div_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return super->div_ops->recalc_rate(div_hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk_hw *div_hw = &super->frac_div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __clk_hw_set_clk(div_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return super->div_ops->set_rate(div_hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void clk_super_restore_context(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk_hw *div_hw = &super->frac_div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int parent_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) parent_id = clk_hw_get_parent_index(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (WARN_ON(parent_id < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) super->div_ops->restore_context(div_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) clk_super_set_parent(hw, parent_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const struct clk_ops tegra_clk_super_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .get_parent = clk_super_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .set_parent = clk_super_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .set_rate = clk_super_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .round_rate = clk_super_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .recalc_rate = clk_super_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .restore_context = clk_super_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk *tegra_clk_register_super_mux(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const char **parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags, void __iomem *reg, u8 clk_super_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct tegra_clk_super_mux *super;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) super = kzalloc(sizeof(*super), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!super)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) init.ops = &tegra_clk_super_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) super->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) super->pllx_index = pllx_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) super->div2_index = div2_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) super->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) super->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) super->flags = clk_super_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) super->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) clk = clk_register(NULL, &super->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kfree(super);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct clk *tegra_clk_register_super_clk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) const char * const *parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long flags, void __iomem *reg, u8 clk_super_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct tegra_clk_super_mux *super;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) super = kzalloc(sizeof(*super), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!super)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) init.ops = &tegra_clk_super_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) super->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) super->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) super->width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) super->flags = clk_super_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) super->frac_div.reg = reg + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) super->frac_div.shift = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) super->frac_div.width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) super->frac_div.frac_width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) super->frac_div.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) super->div_ops = &tegra_clk_frac_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) super->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk = clk_register(NULL, &super->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) kfree(super);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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