^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * based on clk-mux.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DIV_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MUX_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SDMMC_MUL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define get_max_div(d) DIV_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define get_div_field(val) ((val) & DIV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char * const mux_sdmmc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const u8 mux_lj_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const u8 mux_non_lj_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int num_parents, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 src, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const u8 *mux_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) val = readl_relaxed(sdmmc_mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) src = get_mux_field(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (get_div_field(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mux_idx = mux_non_lj_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mux_idx = mux_lj_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (mux_idx[i] == src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) WARN(1, "Unknown parent selector %d\n", src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val = readl_relaxed(sdmmc_mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (get_div_field(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) index = mux_non_lj_idx[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) index = mux_lj_idx[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val &= ~MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) val |= index << MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(val, sdmmc_mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u64 rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val = readl_relaxed(sdmmc_mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) div = get_div_field(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) div += SDMMC_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rate *= SDMMC_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rate += div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) do_div(rate, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long output_rate = req->best_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) req->rate = max(req->rate, req->min_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) req->rate = min(req->rate, req->max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return output_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) req->rate = DIV_ROUND_UP(output_rate * SDMMC_MUL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) div + SDMMC_MUL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) req->rate = output_rate * SDMMC_MUL / (div + SDMMC_MUL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (sdmmc_mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_lock_irqsave(sdmmc_mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) src = clk_sdmmc_mux_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) src = mux_non_lj_idx[src];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) src = mux_lj_idx[src];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val = src << MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val |= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel(val, sdmmc_mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) fence_udelay(2, sdmmc_mux->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (sdmmc_mux->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_unlock_irqrestore(sdmmc_mux->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return gate_ops->is_enabled(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int clk_sdmmc_mux_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return gate_ops->enable(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void clk_sdmmc_mux_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) gate_ops->disable(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void clk_sdmmc_mux_disable_unused(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) gate_ops->disable_unused(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void clk_sdmmc_mux_restore_context(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk_hw *parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long rate = clk_hw_get_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int parent_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) parent_id = clk_hw_get_parent_index(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (WARN_ON(parent_id < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_sdmmc_mux_set_parent(hw, parent_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_sdmmc_mux_set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .get_parent = clk_sdmmc_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .set_parent = clk_sdmmc_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .determine_rate = clk_sdmmc_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .recalc_rate = clk_sdmmc_mux_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .set_rate = clk_sdmmc_mux_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .is_enabled = clk_sdmmc_mux_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .enable = clk_sdmmc_mux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .disable = clk_sdmmc_mux_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .disable_unused = clk_sdmmc_mux_disable_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .restore_context = clk_sdmmc_mux_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long flags, void *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) const struct tegra_clk_periph_regs *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct tegra_sdmmc_mux *sdmmc_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) init.ops = &tegra_clk_sdmmc_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) init.parent_names = mux_sdmmc_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) init.num_parents = ARRAY_SIZE(mux_sdmmc_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bank = get_reg_bank(clk_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!sdmmc_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sdmmc_mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sdmmc_mux->reg = clk_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sdmmc_mux->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sdmmc_mux->gate.clk_base = clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) sdmmc_mux->gate.regs = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sdmmc_mux->gate.clk_num = clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sdmmc_mux->div_flags = div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk = clk_register(NULL, &sdmmc_mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) kfree(sdmmc_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sdmmc_mux->gate.hw.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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