^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PLL_BASE_BYPASS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PLL_BASE_ENABLE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_BASE_REF_ENABLE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLL_BASE_OVERRIDE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLL_BASE_DIVP_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_BASE_DIVP_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLL_BASE_DIVN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_BASE_DIVN_WIDTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_BASE_DIVM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_BASE_DIVM_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLLU_POST_DIVP_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_MISC_DCCON_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_MISC_CPCON_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_MISC_CPCON_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLL_MISC_LFCON_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLL_MISC_LFCON_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLL_MISC_VCOCON_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLL_MISC_VCOCON_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OUT_OF_TABLE_CPCON 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PMC_PLLP_WB0_OVERRIDE 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLL_POST_LOCK_DELAY 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLLDU_LFCON_SET_DIVN 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PLLE_BASE_DIVCML_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PLLE_BASE_DIVCML_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLLE_BASE_DIVP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLLE_BASE_DIVP_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PLLE_BASE_DIVN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PLLE_BASE_DIVN_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLE_BASE_DIVM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLE_BASE_DIVM_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLLE_BASE_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLE_MISC_SETUP_BASE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLLE_MISC_LOCK_ENABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLE_MISC_READY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLLE_MISC_SETUP_EX_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PLLE_MISC_SETUP_EX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLLE_SS_CTRL 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PLLE_SS_CNTL_SSC_BYP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLLE_SS_CNTL_CENTER BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLLE_SS_CNTL_INVERT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PLLE_SS_CNTL_SSC_BYP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PLLE_SS_MAX_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PLLE_SS_MAX_VAL_TEGRA114 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PLLE_SS_MAX_VAL_TEGRA210 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PLLE_SS_INC_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLLE_SS_INC_VAL (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PLLE_SS_COEFFICIENTS_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PLLE_SS_INCINTRV_VAL_TEGRA114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PLLE_SS_INCINTRV_VAL_TEGRA210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PLLE_AUX_PLLP_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PLLE_AUX_USE_LOCKDET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PLLE_AUX_ENABLE_SWCTL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PLLE_AUX_SS_SWCTL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PLLE_AUX_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PLLE_AUX_SEQ_START_STATE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLLE_AUX_PLLRE_SEL BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XUSBIO_PLL_CFG0 0x51c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SATA_PLL_CFG0 0x490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PLLE_MISC_PLLE_PTS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PLLE_MISC_VREG_CTRL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PLLCX_MISC_STROBE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PLLCX_MISC_RESET BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PLLCX_MISC_SDM_DIV_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PLLCX_MISC_FILT_DIV_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PLLCX_MISC_ALPHA_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PLLCX_MISC_DIV_LOW_RANGE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PLLCX_MISC_DIV_HIGH_RANGE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PLLCX_MISC_COEF_LOW_RANGE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PLLCX_MISC_KA_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PLLCX_MISC_KB_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PLLCX_MISC_DIV_LOW_RANGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PLLCX_MISC_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PLLCX_MISC1_DEFAULT 0x000d2308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PLLCX_MISC2_DEFAULT 0x30211200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PLLCX_MISC3_DEFAULT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PMC_SATA_PWRGT 0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PLLSS_MISC_KCP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PLLSS_MISC_KVCO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PLLSS_MISC_SETUP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PLLSS_EN_SDM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PLLSS_EN_SSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PLLSS_EN_DITHER2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PLLSS_EN_DITHER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PLLSS_SDM_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PLLSS_CLAMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PLLSS_SDM_SSC_MAX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PLLSS_SDM_SSC_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PLLSS_SDM_SSC_STEP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PLLSS_SDM_DIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (PLLSS_MISC_KVCO << 24) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PLLSS_MISC_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (PLLSS_EN_SSC << 30) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (PLLSS_EN_DITHER2 << 29) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (PLLSS_EN_DITHER << 28) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (PLLSS_SDM_RESET) << 27 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (PLLSS_CLAMP << 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PLLSS_CTRL1_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PLLSS_CTRL2_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PLLSS_LOCK_OVERRIDE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PLLSS_REF_SRC_SEL_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define UTMIP_PLL_CFG1 0x484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define UTMIP_PLL_CFG2 0x488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define UTMIPLL_HW_PWRDN_CFG0 0x52c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PLLU_HW_PWRDN_CFG0 0x530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define XUSB_PLL_CFG0 0x534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PLLU_BASE_CLKENABLE_USB BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PLLU_BASE_OVERRIDE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define mask(w) ((1 << (w)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define divm_mask(p) mask(p->params->div_nmp->divm_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define divn_mask(p) mask(p->params->div_nmp->divn_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mask(p->params->div_nmp->divp_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define sdm_din_mask(p) p->params->sdm_din_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define divm_shift(p) (p)->params->div_nmp->divm_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define divn_shift(p) (p)->params->div_nmp->divn_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define divp_shift(p) (p)->params->div_nmp->divp_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define divm_max(p) (divm_mask(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define divn_max(p) (divn_mask(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define divp_max(p) (1 << (divp_mask(p)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct div_nmp default_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .divn_shift = PLL_BASE_DIVN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .divn_width = PLL_BASE_DIVN_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .divm_shift = PLL_BASE_DIVM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .divm_width = PLL_BASE_DIVM_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .divp_shift = PLL_BASE_DIVP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .divp_width = PLL_BASE_DIVP_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) val |= BIT(pll->params->lock_enable_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 val, lock_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void __iomem *lock_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) udelay(pll->params->lock_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) lock_addr = pll->clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) lock_addr += pll->params->misc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) lock_addr += pll->params->base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) lock_mask = pll->params->lock_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < pll->params->lock_delay; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val = readl_relaxed(lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if ((val & lock_mask) == lock_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) udelay(PLL_POST_LOCK_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) udelay(2); /* timeout = 2 * lock time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk_hw_get_name(&pll->hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int clk_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Power Management Controller (PMC) can override the PLLM clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * settings, including the enable-state. The PLLM is enabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * PLLM's CaR state is ON and when PLLM isn't gated by PMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return val & PLL_BASE_ENABLE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void _clk_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (pll->params->iddq_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) val = pll_readl(pll->params->iddq_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val &= ~BIT(pll->params->iddq_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pll_writel(val, pll->params->iddq_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (pll->params->reset_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val = pll_readl(pll->params->reset_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val &= ~BIT(pll->params->reset_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pll_writel(val, pll->params->reset_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) clk_pll_enable_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (pll->params->flags & TEGRA_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val &= ~PLL_BASE_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val |= PLL_BASE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (pll->params->flags & TEGRA_PLLM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void _clk_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (pll->params->flags & TEGRA_PLL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) val &= ~PLL_BASE_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) val &= ~PLL_BASE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pll->params->flags & TEGRA_PLLM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (pll->params->reset_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = pll_readl(pll->params->reset_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val |= BIT(pll->params->reset_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pll_writel(val, pll->params->reset_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (pll->params->iddq_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val = pll_readl(pll->params->iddq_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= BIT(pll->params->iddq_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pll_writel(val, pll->params->iddq_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void pll_clk_start_ss(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val |= pll->params->ssc_ctrl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pll_writel(val, pll->params->ssc_ctrl_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val &= ~pll->params->ssc_ctrl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pll_writel(val, pll->params->ssc_ctrl_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int clk_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (clk_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pll_clk_start_ss(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void clk_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pll_clk_stop_ss(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) _clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (p_tohw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) while (p_tohw->pdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (p_div <= p_tohw->pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return p_tohw->hw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) p_tohw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return _p_div_to_hw(&pll->hw, p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (p_tohw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) while (p_tohw->pdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (p_div_hw == p_tohw->hw_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return p_tohw->pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) p_tohw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 1 << p_div_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int _get_table_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct tegra_clk_pll_freq_table *sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (sel->input_rate == parent_rate &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sel->output_rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (sel->input_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (pll->params->pdiv_tohw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) p = _p_div_to_hw(hw, sel->p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (p < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) p = ilog2(sel->p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cfg->input_rate = sel->input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cfg->output_rate = sel->output_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cfg->m = sel->m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cfg->n = sel->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cfg->p = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cfg->cpcon = sel->cpcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cfg->sdm_data = sel->sdm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned long cfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 p_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) switch (parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case 16800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case 9600000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case 28800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * PLL_P_OUT1 rate is not listed in PLLA table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cfreq = parent_rate / (parent_rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pr_err("%s Unexpected reference rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) __func__, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Raise VCO to guarantee 0.5% accuracy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cfg->output_rate <<= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) p_div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cfg->m = parent_rate / cfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cfg->n = cfg->output_rate / cfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cfg->cpcon = OUT_OF_TABLE_CPCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (cfg->m == 0 || cfg->m > divm_max(pll) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cfg->output_rate > pll->params->vco_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cfg->output_rate >>= p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (pll->params->pdiv_tohw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = _p_div_to_hw(hw, 1 << p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cfg->p = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cfg->p = p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * to indicate that SDM is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void clk_pll_set_sdm_data(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct tegra_clk_pll_freq_table *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!pll->params->sdm_din_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (cfg->sdm_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pll_writel_sdm_din(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val = pll_readl_sdm_ctrl(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) enabled = (val & sdm_en_mask(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (cfg->sdm_data == 0 && enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val &= ~pll->params->sdm_ctrl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (cfg->sdm_data != 0 && !enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val |= pll->params->sdm_ctrl_en_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pll_writel_sdm_ctrl(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void _update_pll_mnp(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct tegra_clk_pll_freq_table *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct tegra_clk_pll_params *params = pll->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct div_nmp *div_nmp = params->div_nmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val = pll_override_readl(params->pmc_divp_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val |= cfg->p << div_nmp->override_divp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pll_override_writel(val, params->pmc_divp_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = pll_override_readl(params->pmc_divnm_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) (divn_mask(pll) << div_nmp->override_divn_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val |= (cfg->m << div_nmp->override_divm_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) (cfg->n << div_nmp->override_divn_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pll_override_writel(val, params->pmc_divnm_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) divp_mask_shifted(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val |= (cfg->m << divm_shift(pll)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) (cfg->n << divn_shift(pll)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (cfg->p << divp_shift(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) clk_pll_set_sdm_data(&pll->hw, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void _get_pll_mnp(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct tegra_clk_pll_freq_table *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct tegra_clk_pll_params *params = pll->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct div_nmp *div_nmp = params->div_nmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *cfg = (struct tegra_clk_pll_freq_table) { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val = pll_override_readl(params->pmc_divp_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val = pll_override_readl(params->pmc_divnm_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (pll->params->sdm_din_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val = pll_readl_sdm_din(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) val &= sdm_din_mask(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cfg->sdm_data = sdin_din_to_data(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void _update_pll_cpcon(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (cfg->n >= PLLDU_LFCON_SET_DIVN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val |= 1 << PLL_MISC_LFCON_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val &= ~(1 << PLL_MISC_DCCON_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (rate >= (pll->params->vco_max >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val |= 1 << PLL_MISC_DCCON_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct tegra_clk_pll_freq_table old_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) state = clk_pll_is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (state && pll->params->pre_rate_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = pll->params->pre_rate_change();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) _get_pll_mnp(pll, &old_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = pll->params->dyn_ramp(pll, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pll_clk_stop_ss(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) _clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!pll->params->defaults_set && pll->params->set_defaults)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pll->params->set_defaults(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) _update_pll_mnp(pll, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) _update_pll_cpcon(pll, cfg, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pll_clk_start_ss(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (state && pll->params->post_rate_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pll->params->post_rate_change();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct tegra_clk_pll_freq_table cfg, old_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (pll->params->flags & TEGRA_PLL_FIXED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (rate != pll->params->fixed_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __func__, clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pll->params->fixed_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pr_err("%s: Failed to set %s rate %lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) clk_hw_get_name(hw), rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) _get_pll_mnp(pll, &old_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (pll->params->flags & TEGRA_PLL_VCO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) cfg.p = old_cfg.p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) old_cfg.sdm_data != cfg.sdm_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = _program_pll(hw, &cfg, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct tegra_clk_pll_freq_table cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (pll->params->flags & TEGRA_PLL_FIXED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* PLLM/MB are used for memory; we do not change rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return clk_hw_get_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return pll->params->fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (_get_table_rate(hw, &cfg, rate, *prate) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pll->params->calc_rate(hw, &cfg, rate, *prate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return cfg.output_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct tegra_clk_pll_freq_table cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u64 rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if ((pll->params->flags & TEGRA_PLL_FIXED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) !(val & PLL_BASE_OVERRIDE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct tegra_clk_pll_freq_table sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) parent_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pr_err("Clock %s has unknown fixed frequency\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return pll->params->fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) _get_pll_mnp(pll, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pdiv = _hw_to_p_div(hw, cfg.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (pdiv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk_hw_get_name(hw), cfg.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (pll->params->set_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pll->params->set_gain(&cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) cfg.m *= pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) rate *= cfg.n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) do_div(rate, cfg.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int clk_plle_training(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!pll->pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * PLLE is already disabled, and setup cleared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * create falling edge on PLLE IDDQ input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) val = readl(pll->pmc + PMC_SATA_PWRGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) writel(val, pll->pmc + PMC_SATA_PWRGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) val = readl(pll->pmc + PMC_SATA_PWRGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writel(val, pll->pmc + PMC_SATA_PWRGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) val = readl(pll->pmc + PMC_SATA_PWRGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) writel(val, pll->pmc + PMC_SATA_PWRGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (val & PLLE_MISC_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pr_err("%s: timeout waiting for PLLE\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int clk_plle_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct tegra_clk_pll_freq_table sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) unsigned long input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (clk_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!(val & PLLE_MISC_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err = clk_plle_training(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* configure dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) divm_mask_shifted(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) val |= sel.m << divm_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) val |= sel.n << divn_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) val |= sel.p << divp_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) val |= PLLE_MISC_SETUP_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) val |= PLLE_MISC_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) val = readl(pll->clk_base + PLLE_SS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val &= ~PLLE_SS_COEFFICIENTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) val |= PLLE_SS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) writel(val, pll->clk_base + PLLE_SS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 divn = 0, divm = 0, divp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u64 rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) divm *= divp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rate *= divn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) do_div(rate, divm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static void tegra_clk_pll_restore_context(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct clk_hw *parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) unsigned long parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned long rate = clk_hw_get_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (clk_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (pll->params->set_defaults)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) pll->params->set_defaults(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) clk_pll_set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (!__clk_get_enable_count(hw->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) const struct clk_ops tegra_clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .enable = clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .round_rate = clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .restore_context = tegra_clk_pll_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) const struct clk_ops tegra_clk_plle_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .recalc_rate = clk_plle_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .enable = clk_plle_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * Structure defining the fields for USB UTMI clocks Parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct utmi_clk_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Oscillator Frequency in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 osc_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* UTMIP PLL Enable Delay Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u8 enable_delay_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* UTMIP PLL Stable count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u8 stable_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* UTMIP PLL Active delay count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) u8 active_delay_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* UTMIP PLL Xtal frequency count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) u8 xtal_freq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static const struct utmi_clk_param utmi_parameters[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .osc_frequency = 13000000, .enable_delay_count = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .stable_count = 0x33, .active_delay_count = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .xtal_freq_count = 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .osc_frequency = 19200000, .enable_delay_count = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .stable_count = 0x4b, .active_delay_count = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .xtal_freq_count = 0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .osc_frequency = 12000000, .enable_delay_count = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .stable_count = 0x2f, .active_delay_count = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .xtal_freq_count = 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .osc_frequency = 26000000, .enable_delay_count = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .stable_count = 0x66, .active_delay_count = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .xtal_freq_count = 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .osc_frequency = 16800000, .enable_delay_count = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .stable_count = 0x41, .active_delay_count = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .xtal_freq_count = 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .osc_frequency = 38400000, .enable_delay_count = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .stable_count = 0x0, .active_delay_count = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .xtal_freq_count = 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int clk_pllu_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct clk_hw *pll_ref = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct clk_hw *osc = clk_hw_get_parent(pll_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const struct utmi_clk_param *params = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned long flags = 0, input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!osc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) pr_err("%s: failed to get OSC clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) input_rate = clk_hw_get_rate(osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!clk_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (input_rate == utmi_parameters[i].osc_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) params = &utmi_parameters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pr_err("%s: unexpected input rate %lu Hz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) value = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) value &= ~PLLU_BASE_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pll_writel_base(value, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Program UTMIP PLL stable and active counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Remove power downs from UTMIP PLL control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Program UTMIP PLL delay and oscillator frequency counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Remove power downs from UTMIP PLL control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static const struct clk_ops tegra_clk_pllu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .enable = clk_pllu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .round_rate = clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u16 mdiv = parent_rate / pll_params->cf_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (pll_params->flags & TEGRA_MDIV_NEW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return (!pll_params->mdiv_default ? mdiv :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) min(mdiv, pll_params->mdiv_default));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (pll_params->mdiv_default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return pll_params->mdiv_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (parent_rate > pll_params->cf_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) unsigned int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) int p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) p = DIV_ROUND_UP(pll->params->vco_min, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) cfg->output_rate = rate * p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) cfg->n = cfg->output_rate * cfg->m / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) cfg->input_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) p_div = _p_div_to_hw(hw, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (p_div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) cfg->p = p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) defined(CONFIG_ARCH_TEGRA_124_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) defined(CONFIG_ARCH_TEGRA_132_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return (u16)_pll_fixed_mdiv(pll->params, input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static unsigned long _clip_vco_min(unsigned long vco_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u32 step_a, step_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) switch (parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) step_a = 0x2B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) step_b = 0x0B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) case 16800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) step_a = 0x1A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) step_b = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) step_a = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) step_b = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pr_err("%s: Unexpected reference rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) __func__, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) val = step_a << pll_params->stepa_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) val |= step_b << pll_params->stepb_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int _pll_ramp_calc_pll(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) err = _get_table_rate(hw, cfg, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (cfg->p > pll->params->max_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct tegra_clk_pll_freq_table cfg, old_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) _get_pll_mnp(pll, &old_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (pll->params->flags & TEGRA_PLL_VCO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) cfg.p = old_cfg.p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = _program_pll(hw, &cfg, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct tegra_clk_pll_freq_table cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int ret, p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) u64 output_rate = *prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) p_div = _hw_to_p_div(hw, cfg.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (p_div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return p_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (pll->params->set_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) pll->params->set_gain(&cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) output_rate *= cfg.n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) do_div(output_rate, cfg.m * p_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return output_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static void _pllcx_strobe(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) val |= PLLCX_MISC_STROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) val &= ~PLLCX_MISC_STROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int clk_pllc_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (clk_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) val &= ~PLLCX_MISC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) _pllcx_strobe(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static void _clk_pllc_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) _clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) val |= PLLCX_MISC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static void clk_pllc_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) _clk_pllc_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) unsigned long input_rate, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) u32 val, n_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) switch (input_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) n_threshold = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) n_threshold = 71;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case 16800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) n_threshold = 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) n_threshold = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pr_err("%s: Unexpected reference rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) __func__, input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) val |= n <= n_threshold ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct tegra_clk_pll_freq_table cfg, old_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) _get_pll_mnp(pll, &old_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (cfg.m != old_cfg.m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) state = clk_pll_is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) _clk_pllc_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) _update_pll_mnp(pll, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = clk_pllc_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static long _pllre_calc_rate(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct tegra_clk_pll_freq_table *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u16 m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u64 output_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) m = _pll_fixed_mdiv(pll->params, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) n = rate * m / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) output_rate *= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) do_div(output_rate, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) cfg->m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) cfg->n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return output_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct tegra_clk_pll_freq_table cfg, old_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) int state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) _pllre_calc_rate(pll, &cfg, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) _get_pll_mnp(pll, &old_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) cfg.p = old_cfg.p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) state = clk_pll_is_enabled(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) _clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) _update_pll_mnp(pll, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct tegra_clk_pll_freq_table cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u64 rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) _get_pll_mnp(pll, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) rate *= cfg.n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) do_div(rate, cfg.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return _pllre_calc_rate(pll, NULL, rate, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static int clk_plle_tegra114_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct tegra_clk_pll_freq_table sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) unsigned long input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) val &= ~BIT(29); /* Disable lock override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) val = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) val |= PLLE_AUX_ENABLE_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) val &= ~PLLE_AUX_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pll_writel(val, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) val |= PLLE_MISC_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) val |= PLLE_MISC_IDDQ_SW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) val &= ~PLLE_MISC_IDDQ_SW_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) val |= PLLE_MISC_PLLE_PTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) val = pll_readl(PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) val |= PLLE_SS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) divm_mask_shifted(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) val |= sel.m << divm_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) val |= sel.n << divn_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) val = pll_readl(PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) val &= ~PLLE_SS_COEFFICIENTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) val &= ~PLLE_SS_CNTL_INTERP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* Enable HW control of XUSB brick PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) val &= ~PLLE_MISC_IDDQ_SW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) val = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) pll_writel(val, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) val |= PLLE_AUX_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) pll_writel(val, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) val = pll_readl(XUSBIO_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) XUSBIO_PLL_CFG0_SEQ_START_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) pll_writel(val, XUSBIO_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pll_writel(val, XUSBIO_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* Enable HW control of SATA PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) val = pll_readl(SATA_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) val |= SATA_PLL_CFG0_SEQ_START_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) pll_writel(val, SATA_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) val = pll_readl(SATA_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) val |= SATA_PLL_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) pll_writel(val, SATA_PLL_CFG0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static void clk_plle_tegra114_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) _clk_pll_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static int clk_pllu_tegra114_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) const struct utmi_clk_param *params = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct clk *osc = __clk_lookup("osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) unsigned long flags = 0, input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (!osc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) pr_err("%s: failed to get OSC clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) input_rate = clk_hw_get_rate(__clk_get_hw(osc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (!clk_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) _clk_pll_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (input_rate == utmi_parameters[i].osc_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) params = &utmi_parameters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (!params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) pr_err("%s: unexpected input rate %lu Hz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) input_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) value = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) value &= ~PLLU_BASE_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) pll_writel_base(value, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Program UTMIP PLL stable and active counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /* Remove power downs from UTMIP PLL control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* Program UTMIP PLL delay and oscillator frequency counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* Remove power downs from UTMIP PLL control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* Setup HW control of UTMIPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * to USB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* Enable HW control of UTMIPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) u32 val, val_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* ensure parent is set to pll_ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) val_aux = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (val & PLL_BASE_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) (val_aux & PLLE_AUX_PLLP_SEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) WARN(1, "pll_e enabled with unsupported parent %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) "pll_re_vco");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) pll_writel(val_aux, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) fence_udelay(1, pll->clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) pll->clk_base = clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) pll->pmc = pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pll->params = pll_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) pll->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (!pll_params->div_nmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) pll_params->div_nmp = &default_nmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) const char *name, const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) const struct clk_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Default to _calc_rate if unspecified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (!pll->params->calc_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (pll->params->flags & TEGRA_PLLM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) pll->params->calc_rate = _calc_dynamic_ramp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) pll->params->calc_rate = _calc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (pll->params->set_defaults)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) pll->params->set_defaults(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return clk_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) unsigned long flags, struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) &tegra_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static struct div_nmp pll_e_nmp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .divn_shift = PLLE_BASE_DIVN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .divn_width = PLLE_BASE_DIVN_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .divm_shift = PLLE_BASE_DIVM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .divm_width = PLLE_BASE_DIVM_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .divp_shift = PLLE_BASE_DIVP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .divp_width = PLLE_BASE_DIVP_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) unsigned long flags, struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (!pll_params->div_nmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) pll_params->div_nmp = &pll_e_nmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) &tegra_clk_plle_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) pll_params->flags |= TEGRA_PLLU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) &tegra_clk_pllu_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) defined(CONFIG_ARCH_TEGRA_124_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) defined(CONFIG_ARCH_TEGRA_132_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static const struct clk_ops tegra_clk_pllxc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .enable = clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .round_rate = clk_pll_ramp_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .set_rate = clk_pllxc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static const struct clk_ops tegra_clk_pllc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .enable = clk_pllc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .disable = clk_pllc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .round_rate = clk_pll_ramp_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .set_rate = clk_pllc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static const struct clk_ops tegra_clk_pllre_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .enable = clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .recalc_rate = clk_pllre_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .round_rate = clk_pllre_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .set_rate = clk_pllre_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static const struct clk_ops tegra_clk_plle_tegra114_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .enable = clk_plle_tegra114_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .disable = clk_plle_tegra114_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .enable = clk_pllu_tegra114_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) struct clk *clk, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) u32 val, val_iddq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) parent_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (!pll_params->pdiv_tohw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * If the pll has a set_defaults callback, it will take care of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * configuring dynamic ramping and setting IDDQ in that path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (!pll_params->set_defaults) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) val = readl_relaxed(clk_base + pll_params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (val & PLL_BASE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) val_iddq |= BIT(pll_params->iddq_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) writel_relaxed(val_iddq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) clk_base + pll_params->iddq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) &tegra_clk_pllxc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) spinlock_t *lock, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /* program minimum rate by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (val & PLL_BASE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) BIT(pll_params->iddq_bit_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) m = _pll_fixed_mdiv(pll_params, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) val = m << divm_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /* disable lock override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) val &= ~BIT(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) &tegra_clk_pllre_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) struct clk *clk, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (!pll_params->pdiv_tohw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) parent_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) pll_params->flags |= TEGRA_PLLM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) &tegra_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) struct clk *parent, *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) struct tegra_clk_pll_freq_table cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (!p_tohw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) parent_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * Most of PLLC register fields are shadowed, and can not be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * Initialize PLL to default state: disabled, reset; shadow registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * loaded with default parameters; dividers are preset for half of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * minimum VCO rate (the latter assured that shadowed divider settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * are within supported range).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) cfg.n = cfg.m * pll_params->vco_min / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) while (p_tohw->pdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) if (p_tohw->pdiv == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) cfg.p = p_tohw->hw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) p_tohw++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (!p_tohw->pdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) pll_writel_base(0, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) _update_pll_mnp(pll, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) &tegra_clk_pllc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct clk *tegra_clk_register_plle_tegra114(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) _clk_plle_tegra_init_parent(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) &tegra_clk_plle_tegra114_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) struct clk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) pll_params->flags |= TEGRA_PLLU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) &tegra_clk_pllu_tegra114_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) static const struct clk_ops tegra_clk_pllss_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .is_enabled = clk_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .enable = clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .round_rate = clk_pll_ramp_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .set_rate = clk_pllxc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .restore_context = tegra_clk_pll_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct clk *clk, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) struct tegra_clk_pll_freq_table cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) u32 val, val_iddq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (!pll_params->div_nmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) parent_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) val &= ~PLLSS_REF_SRC_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /* initialize PLL to minimum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) cfg.n = cfg.m * pll_params->vco_min / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) _update_pll_mnp(pll, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (val & PLL_BASE_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) WARN(1, "%s is on but IDDQ set\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) val_iddq |= BIT(pll_params->iddq_bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) val &= ~PLLSS_LOCK_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) &tegra_clk_pllss_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) #if defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct clk *tegra_clk_register_pllre_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) const char *parent_name, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) void __iomem *pmc, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) spinlock_t *lock, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) &tegra_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) return val & PLLE_BASE_ENABLE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static int clk_plle_tegra210_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) struct tegra_clk_pll_freq_table sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) unsigned long input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (clk_plle_tegra210_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) val = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (val & PLLE_AUX_SEQ_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) val &= ~BIT(30); /* Disable lock override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) val |= PLLE_MISC_LOCK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) val |= PLLE_MISC_IDDQ_SW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) val &= ~PLLE_MISC_IDDQ_SW_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) val |= PLLE_MISC_PLLE_PTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) val = pll_readl(PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) val |= PLLE_SS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) divm_mask_shifted(pll));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) val |= sel.m << divm_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) val |= sel.n << divn_shift(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) val |= PLLE_BASE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ret = clk_pll_wait_for_lock(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) val = pll_readl(PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) val &= ~PLLE_SS_COEFFICIENTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) val &= ~PLLE_SS_CNTL_INTERP_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) pll_writel(val, PLLE_SS_CTRL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) val &= ~PLLE_MISC_IDDQ_SW_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) val = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) pll_writel(val, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) val |= PLLE_AUX_SEQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) pll_writel(val, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) static void clk_plle_tegra210_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) val = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (val & PLLE_AUX_SEQ_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) val = pll_readl_base(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) val &= ~PLLE_BASE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) pll_writel_base(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) val = pll_readl(pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) pll_writel(val, pll->params->aux_reg, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) val = pll_readl_misc(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) pll_writel_misc(val, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (pll->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) struct tegra_clk_pll *pll = to_clk_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) _clk_plle_tegra_init_parent(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static const struct clk_ops tegra_clk_plle_tegra210_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .is_enabled = clk_plle_tegra210_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .enable = clk_plle_tegra210_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .disable = clk_plle_tegra210_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .restore_context = tegra_clk_plle_t210_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) struct clk *tegra_clk_register_plle_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) void __iomem *clk_base, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) _clk_plle_tegra_init_parent(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) &tegra_clk_plle_tegra210_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) struct clk *tegra_clk_register_pllc_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) const char *parent_name, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) void __iomem *pmc, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) struct clk *parent, *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (!p_tohw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) &tegra_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) struct clk *tegra_clk_register_pllss_tegra210(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) const char *parent_name, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) struct clk *clk, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (!pll_params->div_nmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) val = readl_relaxed(clk_base + pll_params->base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (val & PLLSS_REF_SRC_SEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) WARN(1, "not supported reference clock for %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) &tegra_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) void __iomem *clk_base, void __iomem *pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) struct tegra_clk_pll_params *pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) struct tegra_clk_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) struct clk *clk, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (!pll_params->pdiv_tohw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) parent = __clk_lookup(parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) WARN(1, "parent clk %s of %s must be registered first\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) parent_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) parent_rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (pll_params->adjust_vco)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) pll_params->vco_min = pll_params->adjust_vco(pll_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) pll_params->flags |= TEGRA_PLL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) pll_params->flags |= TEGRA_PLLMB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (IS_ERR(pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) &tegra_clk_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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