^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define pll_out_enb(p) (BIT(p->enb_bit_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define pll_out_rst(p) (BIT(p->rst_bit_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int clk_pll_out_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 val = readl_relaxed(pll_out->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) state = (val & pll_out_enb(pll_out)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (!(val & (pll_out_rst(pll_out))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int clk_pll_out_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (pll_out->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) spin_lock_irqsave(pll_out->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) val = readl_relaxed(pll_out->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel_relaxed(val, pll_out->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (pll_out->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spin_unlock_irqrestore(pll_out->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void clk_pll_out_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (pll_out->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spin_lock_irqsave(pll_out->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val = readl_relaxed(pll_out->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(val, pll_out->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (pll_out->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spin_unlock_irqrestore(pll_out->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void tegra_clk_pll_out_restore_context(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!__clk_get_enable_count(hw->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clk_pll_out_disable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) clk_pll_out_enable(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct clk_ops tegra_clk_pll_out_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .is_enabled = clk_pll_out_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .enable = clk_pll_out_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .disable = clk_pll_out_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .restore_context = tegra_clk_pll_out_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *tegra_clk_register_pll_out(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct tegra_clk_pll_out *pll_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!pll_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) init.ops = &tegra_clk_pll_out_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pll_out->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pll_out->enb_bit_idx = enb_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pll_out->rst_bit_idx = rst_bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pll_out->flags = pll_out_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pll_out->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pll_out->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk = clk_register(NULL, &pll_out->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) kfree(pll_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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