Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static DEFINE_SPINLOCK(periph_ref_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Macros to assist peripheral gate clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define read_enb(gate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define write_enb_set(val, gate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define write_enb_clr(val, gate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define read_rst(gate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define write_rst_clr(val, gate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LVL2_CLK_GATE_OVRE 0x554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Peripheral gate clock ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int clk_periph_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (!(read_enb(gate) & periph_clk_to_bit(gate)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		if (read_rst(gate) & periph_clk_to_bit(gate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void clk_periph_enable_locked(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	write_enb_set(periph_clk_to_bit(gate), gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	    !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if (read_rst(gate) & periph_clk_to_bit(gate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			udelay(5); /* reset propogation delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			write_rst_clr(periph_clk_to_bit(gate), gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static void clk_periph_disable_locked(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * If peripheral is in the APB bus then read the APB bus to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * flush the write operation in apb bus. This will avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * peripheral access after disabling clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (gate->flags & TEGRA_PERIPH_ON_APB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		tegra_read_chipid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	write_enb_clr(periph_clk_to_bit(gate), gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int clk_periph_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	spin_lock_irqsave(&periph_ref_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (!gate->enable_refcnt[gate->clk_num]++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		clk_periph_enable_locked(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_unlock_irqrestore(&periph_ref_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void clk_periph_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	spin_lock_irqsave(&periph_ref_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	WARN_ON(!gate->enable_refcnt[gate->clk_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (--gate->enable_refcnt[gate->clk_num] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		clk_periph_disable_locked(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	spin_unlock_irqrestore(&periph_ref_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void clk_periph_disable_unused(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	spin_lock_irqsave(&periph_ref_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * Some clocks are duplicated and some of them are marked as critical,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * like fuse and fuse_burn for example, thus the enable_refcnt will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * be non-zero here if the "unused" duplicate is disabled by CCF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (!gate->enable_refcnt[gate->clk_num])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		clk_periph_disable_locked(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	spin_unlock_irqrestore(&periph_ref_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct clk_ops tegra_clk_periph_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.is_enabled = clk_periph_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.enable = clk_periph_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.disable = clk_periph_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.disable_unused = clk_periph_disable_unused,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk *tegra_clk_register_periph_gate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		const char *parent_name, u8 gate_flags, void __iomem *clk_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		unsigned long flags, int clk_num, int *enable_refcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct tegra_clk_periph_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	const struct tegra_clk_periph_regs *pregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	pregs = get_reg_bank(clk_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (!pregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		pr_err("%s: could not allocate periph gate clk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	init.ops = &tegra_clk_periph_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	gate->clk_base = clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	gate->clk_num = clk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	gate->flags = gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	gate->enable_refcnt = enable_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	gate->regs = pregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	clk = clk_register(NULL, &gate->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }