Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) static inline struct tegra_clk_periph_fixed *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) to_tegra_clk_periph_fixed(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	return container_of(hw, struct tegra_clk_periph_fixed, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static int tegra_clk_periph_fixed_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u32 mask = 1 << (fixed->num % 32), value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	value = readl(fixed->base + fixed->regs->enb_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	if (value & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		value = readl(fixed->base + fixed->regs->rst_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		if ((value & mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int tegra_clk_periph_fixed_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 mask = 1 << (fixed->num % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	writel(mask, fixed->base + fixed->regs->enb_set_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static void tegra_clk_periph_fixed_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 mask = 1 << (fixed->num % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	writel(mask, fixed->base + fixed->regs->enb_clr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				   unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	rate = (unsigned long long)parent_rate * fixed->mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	do_div(rate, fixed->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return (unsigned long)rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct clk_ops tegra_clk_periph_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.is_enabled = tegra_clk_periph_fixed_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.enable = tegra_clk_periph_fixed_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.disable = tegra_clk_periph_fixed_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.recalc_rate = tegra_clk_periph_fixed_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct clk *tegra_clk_register_periph_fixed(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 					    const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					    unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					    void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					    unsigned int mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 					    unsigned int div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					    unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	const struct tegra_clk_periph_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct tegra_clk_periph_fixed *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	regs = get_reg_bank(num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	init.parent_names = parent ? &parent : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	init.num_parents = parent ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	init.ops = &tegra_clk_periph_fixed_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	fixed->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	fixed->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	fixed->mul = mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	fixed->div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	fixed->num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	fixed->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	clk = clk_register(NULL, &fixed->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		kfree(fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }