Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This header provides IDs for clocks common between several Tegra SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef _TEGRA_CLK_ID_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define _TEGRA_CLK_ID_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) enum clk_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	tegra_clk_actmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	tegra_clk_adx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	tegra_clk_adx1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	tegra_clk_afi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	tegra_clk_amx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	tegra_clk_amx1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	tegra_clk_apb2ape,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	tegra_clk_ahbdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	tegra_clk_apbdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	tegra_clk_apbif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	tegra_clk_ape,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	tegra_clk_audio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	tegra_clk_audio0_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	tegra_clk_audio0_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	tegra_clk_audio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	tegra_clk_audio1_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	tegra_clk_audio1_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	tegra_clk_audio2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	tegra_clk_audio2_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	tegra_clk_audio2_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	tegra_clk_audio3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	tegra_clk_audio3_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	tegra_clk_audio3_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	tegra_clk_audio4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	tegra_clk_audio4_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	tegra_clk_audio4_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	tegra_clk_bsea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	tegra_clk_bsev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	tegra_clk_cclk_g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	tegra_clk_cclk_lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	tegra_clk_cilab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	tegra_clk_cilcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	tegra_clk_cile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	tegra_clk_clk_32k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	tegra_clk_clk72Mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	tegra_clk_clk72Mhz_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	tegra_clk_clk_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	tegra_clk_osc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	tegra_clk_osc_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	tegra_clk_osc_div4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	tegra_clk_cml0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	tegra_clk_cml1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	tegra_clk_csi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	tegra_clk_csite,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	tegra_clk_csite_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	tegra_clk_csus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	tegra_clk_cve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	tegra_clk_dam0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	tegra_clk_dam1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	tegra_clk_dam2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	tegra_clk_d_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	tegra_clk_dbgapb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	tegra_clk_dds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	tegra_clk_dfll_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	tegra_clk_dfll_soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	tegra_clk_disp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	tegra_clk_disp1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	tegra_clk_disp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	tegra_clk_disp2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	tegra_clk_dp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	tegra_clk_dpaux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	tegra_clk_dpaux1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	tegra_clk_dsialp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	tegra_clk_dsia_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	tegra_clk_dsiblp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	tegra_clk_dsib_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	tegra_clk_dtv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	tegra_clk_emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	tegra_clk_entropy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	tegra_clk_entropy_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	tegra_clk_epp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	tegra_clk_epp_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	tegra_clk_extern1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	tegra_clk_extern2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	tegra_clk_extern3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	tegra_clk_fuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	tegra_clk_fuse_burn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	tegra_clk_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	tegra_clk_gr2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	tegra_clk_gr2d_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tegra_clk_gr3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	tegra_clk_gr3d_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	tegra_clk_hclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	tegra_clk_hda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	tegra_clk_hda_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	tegra_clk_hda2codec_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	tegra_clk_hda2codec_2x_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	tegra_clk_hda2hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	tegra_clk_hdmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	tegra_clk_hdmi_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	tegra_clk_host1x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	tegra_clk_host1x_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	tegra_clk_host1x_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	tegra_clk_hsic_trk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tegra_clk_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tegra_clk_i2c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	tegra_clk_i2c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tegra_clk_i2c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tegra_clk_i2c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	tegra_clk_i2c6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tegra_clk_i2cslow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	tegra_clk_i2s0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	tegra_clk_i2s0_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	tegra_clk_i2s1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	tegra_clk_i2s1_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	tegra_clk_i2s2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	tegra_clk_i2s2_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	tegra_clk_i2s3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	tegra_clk_i2s3_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	tegra_clk_i2s4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	tegra_clk_i2s4_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tegra_clk_isp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	tegra_clk_isp_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	tegra_clk_isp_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	tegra_clk_ispb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	tegra_clk_kbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	tegra_clk_kfuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	tegra_clk_la,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	tegra_clk_maud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	tegra_clk_mipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	tegra_clk_mipibif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	tegra_clk_mipi_cal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	tegra_clk_mpe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tegra_clk_mselect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	tegra_clk_msenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	tegra_clk_ndflash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	tegra_clk_ndflash_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	tegra_clk_ndspeed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	tegra_clk_ndspeed_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	tegra_clk_nor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	tegra_clk_nvdec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	tegra_clk_nvenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	tegra_clk_nvjpg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tegra_clk_owr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	tegra_clk_owr_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	tegra_clk_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	tegra_clk_pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	tegra_clk_pll_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	tegra_clk_pll_a_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	tegra_clk_pll_a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	tegra_clk_pll_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tegra_clk_pll_c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tegra_clk_pll_c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	tegra_clk_pll_c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tegra_clk_pll_c4_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tegra_clk_pll_c4_out1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	tegra_clk_pll_c4_out2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tegra_clk_pll_c4_out3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	tegra_clk_pll_c_out1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	tegra_clk_pll_d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	tegra_clk_pll_d2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	tegra_clk_pll_d2_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tegra_clk_pll_d_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	tegra_clk_pll_dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	tegra_clk_pll_e_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	tegra_clk_pll_g_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	tegra_clk_pll_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tegra_clk_pll_m_out1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	tegra_clk_pll_mb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	tegra_clk_pll_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tegra_clk_pll_p_out1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	tegra_clk_pll_p_out2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	tegra_clk_pll_p_out2_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	tegra_clk_pll_p_out3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	tegra_clk_pll_p_out4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	tegra_clk_pll_p_out4_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tegra_clk_pll_p_out5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	tegra_clk_pll_p_out_hsio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	tegra_clk_pll_p_out_xusb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	tegra_clk_pll_p_out_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	tegra_clk_pll_p_out_adsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	tegra_clk_pll_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	tegra_clk_pll_re_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	tegra_clk_pll_re_vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	tegra_clk_pll_u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	tegra_clk_pll_u_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	tegra_clk_pll_u_out1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	tegra_clk_pll_u_out2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	tegra_clk_pll_u_12m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	tegra_clk_pll_u_480m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	tegra_clk_pll_u_48m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	tegra_clk_pll_u_60m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	tegra_clk_pll_x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	tegra_clk_pll_x_out0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tegra_clk_pwm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	tegra_clk_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	tegra_clk_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	tegra_clk_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	tegra_clk_sata_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	tegra_clk_sata_cold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	tegra_clk_sata_oob,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	tegra_clk_sata_oob_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	tegra_clk_sbc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	tegra_clk_sbc1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	tegra_clk_sbc1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	tegra_clk_sbc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	tegra_clk_sbc2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	tegra_clk_sbc2_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	tegra_clk_sbc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	tegra_clk_sbc3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	tegra_clk_sbc3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	tegra_clk_sbc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	tegra_clk_sbc4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	tegra_clk_sbc4_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	tegra_clk_sbc5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	tegra_clk_sbc5_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	tegra_clk_sbc6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	tegra_clk_sbc6_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	tegra_clk_sclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	tegra_clk_sdmmc_legacy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	tegra_clk_sdmmc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	tegra_clk_sdmmc1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	tegra_clk_sdmmc1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	tegra_clk_sdmmc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	tegra_clk_sdmmc2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	tegra_clk_sdmmc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	tegra_clk_sdmmc3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	tegra_clk_sdmmc3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	tegra_clk_sdmmc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	tegra_clk_sdmmc4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	tegra_clk_se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	tegra_clk_se_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	tegra_clk_soc_therm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	tegra_clk_soc_therm_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	tegra_clk_sor0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	tegra_clk_sor0_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	tegra_clk_sor1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	tegra_clk_sor1_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	tegra_clk_spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	tegra_clk_spdif_2x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	tegra_clk_spdif_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	tegra_clk_spdif_in_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	tegra_clk_spdif_in_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	tegra_clk_spdif_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	tegra_clk_spdif_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	tegra_clk_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	tegra_clk_trace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	tegra_clk_tsec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	tegra_clk_tsec_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	tegra_clk_tsecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	tegra_clk_tsensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	tegra_clk_tvdac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	tegra_clk_tvo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	tegra_clk_uarta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	tegra_clk_uarta_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	tegra_clk_uartb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	tegra_clk_uartb_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	tegra_clk_uartc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	tegra_clk_uartc_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	tegra_clk_uartd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	tegra_clk_uartd_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	tegra_clk_uarte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	tegra_clk_uarte_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	tegra_clk_uartape,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	tegra_clk_usb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	tegra_clk_usb2_hsic_trk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	tegra_clk_usb2_trk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	tegra_clk_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	tegra_clk_usbd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	tegra_clk_vcp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	tegra_clk_vde,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	tegra_clk_vde_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	tegra_clk_vfir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	tegra_clk_vi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	tegra_clk_vi_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	tegra_clk_vi_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	tegra_clk_vi_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	tegra_clk_vi_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	tegra_clk_vic03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	tegra_clk_vic03_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	tegra_clk_vim2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	tegra_clk_vimclk_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	tegra_clk_vi_sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	tegra_clk_vi_sensor_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	tegra_clk_vi_sensor_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	tegra_clk_vi_sensor2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	tegra_clk_vi_sensor2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	tegra_clk_xusb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	tegra_clk_xusb_dev_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	tegra_clk_xusb_dev_src_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	tegra_clk_xusb_falcon_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	tegra_clk_xusb_falcon_src_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	tegra_clk_xusb_fs_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	tegra_clk_xusb_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	tegra_clk_xusb_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	tegra_clk_xusb_host_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	tegra_clk_xusb_host_src_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	tegra_clk_xusb_hs_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	tegra_clk_xusb_hs_src_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	tegra_clk_xusb_ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	tegra_clk_xusb_ss_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	tegra_clk_xusb_ss_src_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	tegra_clk_xusb_ss_div2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	tegra_clk_xusb_ssp_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	tegra_clk_sclk_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	tegra_clk_sor_safe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	tegra_clk_cec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	tegra_clk_ispa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	tegra_clk_dmic1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	tegra_clk_dmic2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	tegra_clk_dmic3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	tegra_clk_dmic1_sync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	tegra_clk_dmic2_sync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	tegra_clk_dmic3_sync_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	tegra_clk_dmic1_sync_clk_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	tegra_clk_dmic2_sync_clk_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	tegra_clk_dmic3_sync_clk_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	tegra_clk_iqc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	tegra_clk_iqc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	tegra_clk_pll_a_out_adsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	tegra_clk_pll_a_out0_out_adsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	tegra_clk_adsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	tegra_clk_adsp_neon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	tegra_clk_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif	/* _TEGRA_CLK_ID_H */