^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clk-dfll.c - Tegra DFLL clock source common code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Aleksandr Frid <afrid@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley <pwalmsley@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This library is for the DVCO and DFLL IP blocks on the Tegra124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * SoC. These IP blocks together are also known at NVIDIA as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * "CL-DVFS". To try to avoid confusion, this code refers to them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * collectively as the "DFLL."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The DFLL is a root clocksource which tolerates some amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * supply voltage noise. Tegra124 uses it to clock the fast CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * complex when the target CPU speed is above a particular rate. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DFLL can be operated in either open-loop mode or closed-loop mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * In open-loop mode, the DFLL generates an output clock appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * to the supply voltage. In closed-loop mode, when configured with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * target frequency, the DFLL minimizes supply voltage while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * delivering an average frequency equal to the target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Devices clocked by the DFLL must be able to tolerate frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * variation. In the case of the CPU, it's important to note that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * CPU cycle time will vary. This has implications for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * performance-measurement code and any code that relies on the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * cycle time to delay for a certain length of time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "clk-dfll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "cvb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * DFLL control registers - access via dfll_{readl,writel}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* DFLL_CTRL: DFLL control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DFLL_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DFLL_CTRL_MODE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* DFLL_CONFIG: DFLL sample rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DFLL_CONFIG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DFLL_CONFIG_DIV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DFLL_CONFIG_DIV_PRESCALE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* DFLL_PARAMS: tuning coefficients for closed loop integrator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DFLL_PARAMS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DFLL_PARAMS_CG_SCALE (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DFLL_PARAMS_FORCE_MODE_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DFLL_PARAMS_CF_PARAM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DFLL_PARAMS_CI_PARAM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DFLL_PARAMS_CG_PARAM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* DFLL_TUNE0: delay line configuration register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DFLL_TUNE0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* DFLL_TUNE1: delay line configuration register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DFLL_TUNE1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* DFLL_FREQ_REQ: target DFLL frequency control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DFLL_FREQ_REQ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DFLL_FREQ_REQ_FORCE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FORCE_MAX 2047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FORCE_MIN -2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DFLL_FREQ_REQ_SCALE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DFLL_FREQ_REQ_SCALE_MAX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DFLL_FREQ_REQ_MULT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FREQ_MAX 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* DFLL_DROOP_CTRL: droop prevention control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DFLL_DROOP_CTRL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* DFLL_OUTPUT_CFG: closed loop mode control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* NOTE: access via dfll_i2c_{readl,writel} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DFLL_OUTPUT_CFG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OUT_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DFLL_OUTPUT_CFG_SAFE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DFLL_OUTPUT_CFG_SAFE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DFLL_OUTPUT_CFG_MAX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DFLL_OUTPUT_CFG_MAX_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DFLL_OUTPUT_CFG_MIN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DFLL_OUTPUT_CFG_MIN_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DFLL_OUTPUT_CFG_PWM_DIV_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DFLL_OUTPUT_FORCE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DFLL_OUTPUT_FORCE_VALUE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* DFLL_MONITOR_CTRL: internal monitor data source control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DFLL_MONITOR_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DFLL_MONITOR_CTRL_FREQ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* DFLL_MONITOR_DATA: internal monitor data output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DFLL_MONITOR_DATA 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DFLL_MONITOR_DATA_VAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * I2C output control registers - access via dfll_i2c_{readl,writel}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* DFLL_I2C_CFG: I2C controller configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DFLL_I2C_CFG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DFLL_I2C_CFG_HS_CODE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DFLL_I2C_CFG_SIZE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DFLL_I2C_VDD_REG_ADDR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* DFLL_I2C_STS: I2C controller status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DFLL_I2C_STS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DFLL_I2C_STS_I2C_LAST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DFLL_I2C_STS_I2C_REQ_PENDING 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* DFLL_INTR_STS: DFLL interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DFLL_INTR_STS 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* DFLL_INTR_EN: DFLL interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DFLL_INTR_EN 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DFLL_INTR_MIN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DFLL_INTR_MAX_MASK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Integrated I2C controller registers - relative to td->i2c_controller_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DFLL_I2C_CLK_DIVISOR 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DFLL_I2C_CLK_DIVISOR_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DFLL_I2C_CLK_DIVISOR_PREDIV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Other constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MAX_DFLL_VOLTAGES 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * integrates the DVCO counter over - used for debug rate monitoring and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * droop control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define REF_CLK_CYC_PER_DVCO_SAMPLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * driver, in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define REF_CLOCK_RATE 51000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * enum dfll_ctrl_mode - DFLL hardware operating mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @DFLL_DISABLED: DFLL not generating an output clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * the requested rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * The integer corresponding to the last two states, minus one, is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * written to the DFLL hardware to change operating modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum dfll_ctrl_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DFLL_UNINITIALIZED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DFLL_DISABLED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DFLL_OPEN_LOOP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DFLL_CLOSED_LOOP = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * enum dfll_tune_range - voltage range that the driver believes it's in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Some DFLL tuning parameters may need to change depending on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * DVCO's voltage; these states represent the ranges that the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * supports. These are software states; these values are never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * written into registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum dfll_tune_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DFLL_TUNE_UNINITIALIZED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DFLL_TUNE_LOW = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) enum tegra_dfll_pmu_if {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TEGRA_DFLL_PMU_I2C = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TEGRA_DFLL_PMU_PWM = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * struct dfll_rate_req - target DFLL rate request data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @rate: target frequency, after the postscaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @dvco_target_rate: target frequency, after the postscaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct dfll_rate_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long dvco_target_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int lut_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 mult_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 scale_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct tegra_dfll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct tegra_dfll_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void __iomem *i2c_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void __iomem *i2c_controller_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __iomem *lut_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct regulator *vdd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct clk *soc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk *i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct clk *dfll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct reset_control *dvco_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long i2c_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long dvco_rate_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) enum dfll_ctrl_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum dfll_tune_range tune_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct dentry *debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct clk_hw dfll_clk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const char *output_clock_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct dfll_rate_req last_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long last_unrounded_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Parameters from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 droop_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 force_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bool cg_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* I2C interface parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 i2c_fs_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 i2c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 i2c_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* lut array entries are regulator framework selectors or PWM values*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned lut[MAX_DFLL_VOLTAGES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long lut_uv[MAX_DFLL_VOLTAGES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int lut_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 lut_bottom, lut_min, lut_max, lut_safe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* PWM interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) enum tegra_dfll_pmu_if pmu_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long pwm_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct pinctrl *pwm_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct pinctrl_state *pwm_enable_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct pinctrl_state *pwm_disable_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 reg_init_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* mode_name: map numeric DFLL modes to names for friendly console messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char * const mode_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [DFLL_UNINITIALIZED] = "uninitialized",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [DFLL_DISABLED] = "disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [DFLL_OPEN_LOOP] = "open_loop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [DFLL_CLOSED_LOOP] = "closed_loop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Register accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return __raw_readl(td->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) WARN_ON(offs >= DFLL_I2C_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __raw_writel(val, td->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static inline void dfll_wmb(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dfll_readl(td, DFLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* I2C output control registers - for addresses above DFLL_I2C_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return __raw_readl(td->i2c_base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __raw_writel(val, td->i2c_base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static inline void dfll_i2c_wmb(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dfll_i2c_readl(td, DFLL_I2C_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * dfll_is_running - is the DFLL currently generating a clock?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * If the DFLL is currently generating an output clock signal, return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * true; otherwise return false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static bool dfll_is_running(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return td->mode >= DFLL_OPEN_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Runtime PM suspend/resume callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @dev: DFLL device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Enable all clocks needed by the DFLL. Assumes that clk_prepare()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * has already been called on all the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * XXX Should also handle context restore when returning from off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int tegra_dfll_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct tegra_dfll *td = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = clk_enable(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(dev, "could not enable ref clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = clk_enable(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dev, "could not enable register clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk_disable(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = clk_enable(td->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(dev, "could not enable i2c clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) clk_disable(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) clk_disable(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) EXPORT_SYMBOL(tegra_dfll_runtime_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @dev: DFLL device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Disable all clocks needed by the DFLL. Assumes that other code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * will later call clk_unprepare().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int tegra_dfll_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct tegra_dfll *td = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk_disable(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) clk_disable(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clk_disable(td->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) EXPORT_SYMBOL(tegra_dfll_runtime_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * DFLL tuning operations (per-voltage-range tuning settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Tune the DFLL oscillator parameters and the CPU clock shaper for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * the low-voltage range. These settings are valid for any voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * but may not be optimal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void dfll_tune_low(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) td->tune_range = DFLL_TUNE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (td->soc->set_clock_trimmers_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) td->soc->set_clock_trimmers_low();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Output clock scaler helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * @dvco_rate: the DVCO rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Apply the same scaling formula that the DFLL hardware uses to scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * the DVCO rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static unsigned long dfll_scale_dvco_rate(int scale_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned long dvco_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * DFLL mode switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * dfll_set_mode - change the DFLL control mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * @mode: DFLL control mode (see enum dfll_ctrl_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Change the DFLL's operating mode between disabled, open-loop mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * and closed-loop mode, or vice versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void dfll_set_mode(struct tegra_dfll *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) enum dfll_ctrl_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) td->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dfll_writel(td, mode - 1, DFLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * DVCO rate control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned long rate, prev_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned long uv, min_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) min_uv = td->lut_uv[out_min];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) for (rate = 0, prev_rate = 0; ; rate++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (IS_ERR(opp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) uv = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (uv && uv > min_uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return prev_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) prev_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return prev_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * DFLL-to-I2C controller interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @enable: whether to enable or disable the I2C voltage requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Set the master enable control for I2C control value updates. If disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * then I2C control messages are inhibited, regardless of the DFLL mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val |= DFLL_OUTPUT_CFG_I2C_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dfll_i2c_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * DFLL-to-PWM controller interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @enable: whether to enable or disable the PWM voltage requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Set the master enable control for PWM control value updates. If disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * then the PWM signal is not driven. Also configure the PWM output pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * to the appropriate state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 val, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(td->dev, "setting enable state failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val = dfll_readl(td, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) & DFLL_OUTPUT_CFG_PWM_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dfll_writel(td, val, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val |= DFLL_OUTPUT_CFG_PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dfll_writel(td, val, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_warn(td->dev, "setting disable state failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) val = dfll_readl(td, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dfll_writel(td, val, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * dfll_set_force_output_value - set fixed value for force output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * @out_val: value to force output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Set the fixed value for force output, DFLL will output this value when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * force output is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dfll_writel(td, val, DFLL_OUTPUT_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return dfll_readl(td, DFLL_OUTPUT_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * dfll_set_force_output_enabled - enable/disable force output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @enable: whether to enable or disable the force output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Set the enable control for fouce output with fixed value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) val |= DFLL_OUTPUT_FORCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) val &= ~DFLL_OUTPUT_FORCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dfll_writel(td, val, DFLL_OUTPUT_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * dfll_force_output - force output a fixed value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @out_sel: value to force output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Set the fixed value for force output, DFLL will output this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (out_sel > OUT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) val = dfll_set_force_output_value(td, out_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if ((td->mode < DFLL_CLOSED_LOOP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) !(val & DFLL_OUTPUT_FORCE_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dfll_set_force_output_enabled(td, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * dfll_load_lut - load the voltage lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @td: struct tegra_dfll *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Load the voltage-to-PMIC register value lookup table into the DFLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * IP block memory. Look-up tables can be loaded at any time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void dfll_load_i2c_lut(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int i, lut_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (i < td->lut_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) lut_index = td->lut_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else if (i > td->lut_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) lut_index = td->lut_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) lut_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val = regulator_list_hardware_vsel(td->vdd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) td->lut[lut_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __raw_writel(val, td->lut_base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dfll_i2c_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * During DFLL driver initialization, program the DFLL-I2C interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * with the PMU slave address, vdd register offset, and transfer mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * This data is used by the DFLL to automatically construct I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * voltage-set commands, which are then passed to the DFLL's internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * I2C controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void dfll_init_i2c_if(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (td->i2c_slave_addr > 0x7f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val |= DFLL_I2C_CFG_SLAVE_ADDR_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val |= DFLL_I2C_CFG_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) val |= DFLL_I2C_CFG_ARB_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dfll_i2c_writel(td, val, DFLL_I2C_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* default hs divisor just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dfll_i2c_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * dfll_init_out_if - prepare DFLL-to-PMIC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * During DFLL driver initialization or resume from context loss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * disable the I2C command output to the PMIC, set safe voltage and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * output limits, and disable and clear limit interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void dfll_init_out_if(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) td->lut_min = td->lut_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) td->lut_max = td->lut_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* clear DFLL_OUTPUT_CFG before setting new value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dfll_writel(td, 0, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dfll_writel(td, val, DFLL_OUTPUT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dfll_i2c_writel(td, 0, DFLL_INTR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) DFLL_INTR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 vinit = td->reg_init_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int vstep = td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned long vmin = td->lut_uv[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* set initial voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if ((vinit >= vmin) && vstep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) vsel = DIV_ROUND_UP((vinit - vmin), vstep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dfll_force_output(td, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dfll_load_i2c_lut(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dfll_init_i2c_if(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * Set/get the DFLL's targeted output clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @rate: clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Determines the index of a I2C LUT entry for a voltage that approximately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * produces the given DFLL clock rate. This is used when forcing a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * to the integrator during rate changes. Returns -ENOENT if a suitable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * LUT index is not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int i, align_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (IS_ERR(opp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) for (i = td->lut_bottom; i < td->lut_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * @req: DFLL-rate-request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * @rate: the desired DFLL rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * Populate the DFLL-rate-request record @req fields with the scale_bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * and mult_bits fields, based on the target input rate. Returns 0 upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * success, or -EINVAL if the requested rate in req->rate is too high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * or low for the DFLL to generate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int dfll_calculate_rate_request(struct tegra_dfll *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct dfll_rate_req *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * If requested rate is below the minimum DVCO rate, active the scaler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * In the future the DVCO minimum voltage should be selected based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * chip temperature and the actual minimum rate should be calibrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (rate < td->dvco_rate_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) td->dvco_rate_min / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(td->dev, "%s: Rate %lu is too low\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) req->scale_bits = scale - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rate = td->dvco_rate_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Convert requested rate into frequency request and scale settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (val > FREQ_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(td->dev, "%s: Rate %lu is above dfll range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) req->mult_bits = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) req->rate = dfll_scale_dvco_rate(req->scale_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) req->dvco_target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (req->lut_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return req->lut_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * dfll_set_frequency_request - start the frequency change operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * @req: rate request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * Tell the DFLL to try to change its output frequency to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * frequency represented by @req. DFLL must be in closed-loop mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static void dfll_set_frequency_request(struct tegra_dfll *td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct dfll_rate_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int force_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int coef = 128; /* FIXME: td->cg_scale? */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) force_val = (req->lut_index - td->lut_safe) * coef / td->cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DFLL_FREQ_REQ_FORCE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dfll_writel(td, val, DFLL_FREQ_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * tegra_dfll_request_rate - set the next rate for the DFLL to tune to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * @rate: clock rate to target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Convert the requested clock rate @rate into the DFLL control logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * settings. In closed-loop mode, update new settings immediately to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * adjust DFLL output rate accordingly. Otherwise, just save them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * until the next switch to closed loop. Returns 0 upon success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * if @rate is outside the DFLL's tunable range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct dfll_rate_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (td->mode == DFLL_UNINITIALIZED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) __func__, mode_name[td->mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = dfll_calculate_rate_request(td, &req, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) td->last_unrounded_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) td->last_req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (td->mode == DFLL_CLOSED_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dfll_set_frequency_request(td, &td->last_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * DFLL enable/disable & open-loop <-> closed-loop transitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * dfll_disable - switch from open-loop mode to disabled mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * or -EPERM if the DFLL is not currently in open-loop mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int dfll_disable(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (td->mode != DFLL_OPEN_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(td->dev, "cannot disable DFLL in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mode_name[td->mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dfll_set_mode(td, DFLL_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pm_runtime_put_sync(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * dfll_enable - switch a disabled DFLL to open-loop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * or -EPERM if the DFLL is not currently disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int dfll_enable(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (td->mode != DFLL_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_err(td->dev, "cannot enable DFLL in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mode_name[td->mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pm_runtime_get_sync(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dfll_set_mode(td, DFLL_OPEN_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * dfll_set_open_loop_config - prepare to switch to open-loop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Prepare to switch the DFLL to open-loop mode. This switches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * DFLL to the low-voltage tuning range, ensures that I2C output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * forcing is disabled, and disables the output clock rate scaler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * The DFLL's low-voltage tuning range parameters must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * characterized to keep the downstream device stable at any DVCO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * input voltage. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void dfll_set_open_loop_config(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* always tune low (safe) in open loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (td->tune_range != DFLL_TUNE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dfll_tune_low(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val = dfll_readl(td, DFLL_FREQ_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) val |= DFLL_FREQ_REQ_SCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) val &= ~DFLL_FREQ_REQ_FORCE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dfll_writel(td, val, DFLL_FREQ_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dfll_wmb(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * tegra_dfll_lock - switch from open-loop to closed-loop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * DFLL is not currently in open-loop mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int dfll_lock(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct dfll_rate_req *req = &td->last_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) switch (td->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case DFLL_CLOSED_LOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case DFLL_OPEN_LOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (req->rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dfll_pwm_set_output_enabled(td, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dfll_i2c_set_output_enabled(td, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dfll_set_mode(td, DFLL_CLOSED_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dfll_set_frequency_request(td, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dfll_set_force_output_enabled(td, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) BUG_ON(td->mode > DFLL_CLOSED_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __func__, mode_name[td->mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * tegra_dfll_unlock - switch from closed-loop to open-loop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * or -EPERM if the DFLL is not currently in open-loop mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int dfll_unlock(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) switch (td->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) case DFLL_CLOSED_LOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dfll_set_open_loop_config(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dfll_set_mode(td, DFLL_OPEN_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dfll_pwm_set_output_enabled(td, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dfll_i2c_set_output_enabled(td, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) case DFLL_OPEN_LOOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) BUG_ON(td->mode > DFLL_CLOSED_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) __func__, mode_name[td->mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * Clock framework integration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * When the DFLL is being controlled by the CCF, always enter closed loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * mode when the clk is enabled. This requires that a DFLL rate request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * has been set beforehand, which implies that a clk_set_rate() call is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * always required before a clk_enable().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int dfll_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct tegra_dfll *td = clk_hw_to_dfll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return dfll_is_running(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int dfll_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct tegra_dfll *td = clk_hw_to_dfll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ret = dfll_enable(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ret = dfll_lock(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dfll_disable(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static void dfll_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct tegra_dfll *td = clk_hw_to_dfll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret = dfll_unlock(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dfll_disable(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct tegra_dfll *td = clk_hw_to_dfll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return td->last_unrounded_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int dfll_clk_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct clk_rate_request *clk_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct tegra_dfll *td = clk_hw_to_dfll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct dfll_rate_req req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * Don't set the rounded rate, since it doesn't really matter as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * the output rate will be voltage controlled anyway, and cpufreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * freaks out if any rounding happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct tegra_dfll *td = clk_hw_to_dfll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return dfll_request_rate(td, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static const struct clk_ops dfll_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .is_enabled = dfll_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .enable = dfll_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .disable = dfll_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .recalc_rate = dfll_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .determine_rate = dfll_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .set_rate = dfll_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static struct clk_init_data dfll_clk_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .ops = &dfll_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .num_parents = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * dfll_register_clk - register the DFLL output clock with the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Register the DFLL's output clock with the Linux clock framework and register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * or -ENOMEM upon failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int dfll_register_clk(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dfll_clk_init_data.name = td->output_clock_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) td->dfll_clk_hw.init = &dfll_clk_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (IS_ERR(td->dfll_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_err(td->dev, "DFLL clock registration error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) td->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(td->dev, "of_clk_add_provider() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) clk_unregister(td->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * dfll_unregister_clk - unregister the DFLL output clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * Unregister the DFLL's output clock from the Linux clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * and from clkdev. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static void dfll_unregister_clk(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) of_clk_del_provider(td->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) clk_unregister(td->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) td->dfll_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * Debugfs interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * Monitor control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * @ref_rate: DFLL reference clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * per second. Returns the converted value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static u64 dfll_calc_monitored_rate(u32 monitor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) unsigned long ref_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * If the DFLL is enabled, return the last rate reported by the DFLL's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * internal monitoring hardware. This works in both open-loop and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * closed-loop mode, and takes the output scaler setting into account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * Assumes that the monitor was programmed to monitor frequency before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * the sample period started. If the driver believes that the DFLL is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * currently uninitialized or disabled, it will return 0, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * otherwise the DFLL monitor data register will return the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * measured rate from when the DFLL was active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 v, s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u64 pre_scaler_rate, post_scaler_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (!dfll_is_running(td))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) v = dfll_readl(td, DFLL_MONITOR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) s = dfll_readl(td, DFLL_FREQ_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return post_scaler_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static int attr_enable_get(void *data, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct tegra_dfll *td = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) *val = dfll_is_running(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int attr_enable_set(void *data, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct tegra_dfll *td = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return val ? dfll_enable(td) : dfll_disable(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) DEFINE_DEBUGFS_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static int attr_lock_get(void *data, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct tegra_dfll *td = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) *val = (td->mode == DFLL_CLOSED_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int attr_lock_set(void *data, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct tegra_dfll *td = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return val ? dfll_lock(td) : dfll_unlock(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) DEFINE_DEBUGFS_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static int attr_rate_get(void *data, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct tegra_dfll *td = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) *val = dfll_read_monitor_rate(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int attr_rate_set(void *data, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct tegra_dfll *td = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return dfll_request_rate(td, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) DEFINE_DEBUGFS_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static int attr_registers_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) u32 val, offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct tegra_dfll *td = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) seq_puts(s, "CONTROL REGISTERS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (offs == DFLL_OUTPUT_CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) val = dfll_i2c_readl(td, offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) val = dfll_readl(td, offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) seq_puts(s, "\nI2C and INTR REGISTERS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dfll_i2c_readl(td, offs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dfll_i2c_readl(td, offs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) offs = DFLL_I2C_CLK_DIVISOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) __raw_readl(td->i2c_controller_base + offs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) seq_puts(s, "\nLUT:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) __raw_readl(td->lut_base + offs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) DEFINE_SHOW_ATTRIBUTE(attr_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static void dfll_debug_init(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!td || (td->mode == DFLL_UNINITIALIZED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) td->debugfs_dir = root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) debugfs_create_file_unsafe("enable", 0644, root, td,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) &enable_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static void inline dfll_debug_init(struct tegra_dfll *td) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #endif /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * DFLL initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * dfll_set_default_params - program non-output related DFLL parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * During DFLL driver initialization or resume from context loss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * program parameters for the closed loop integrator, DVCO tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * voltage droop control and monitor control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void dfll_set_default_params(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) BUG_ON(val > DFLL_CONFIG_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dfll_writel(td, val, DFLL_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dfll_writel(td, val, DFLL_PARAMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dfll_tune_low(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * dfll_init_clks - clk_get() the DFLL source clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * Call clk_get() on the DFLL source clocks and save the pointers for later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * use. Returns 0 upon success or error (see devm_clk_get) if one or more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * of the clocks couldn't be looked up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int dfll_init_clks(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) td->ref_clk = devm_clk_get(td->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (IS_ERR(td->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dev_err(td->dev, "missing ref clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return PTR_ERR(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) td->soc_clk = devm_clk_get(td->dev, "soc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (IS_ERR(td->soc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_err(td->dev, "missing soc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return PTR_ERR(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) td->i2c_clk = devm_clk_get(td->dev, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (IS_ERR(td->i2c_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dev_err(td->dev, "missing i2c clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return PTR_ERR(td->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) td->i2c_clk_rate = clk_get_rate(td->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * dfll_init - Prepare the DFLL IP block for use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Do everything necessary to prepare the DFLL IP block for use. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * DFLL will be left in DISABLED state. Called by dfll_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * Returns 0 upon success, or passes along the error from whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * function returned it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static int dfll_init(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) td->ref_rate = clk_get_rate(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (td->ref_rate != REF_CLOCK_RATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) td->ref_rate, REF_CLOCK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) reset_control_deassert(td->dvco_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ret = clk_prepare(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_err(td->dev, "failed to prepare ref_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ret = clk_prepare(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) dev_err(td->dev, "failed to prepare soc_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) goto di_err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ret = clk_prepare(td->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev_err(td->dev, "failed to prepare i2c_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) goto di_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) td->last_unrounded_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) pm_runtime_enable(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pm_runtime_get_sync(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dfll_set_mode(td, DFLL_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dfll_set_default_params(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (td->soc->init_clock_trimmers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) td->soc->init_clock_trimmers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dfll_set_open_loop_config(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dfll_init_out_if(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pm_runtime_put_sync(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) di_err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) clk_unprepare(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) di_err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) clk_unprepare(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) reset_control_assert(td->dvco_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * tegra_dfll_suspend - check DFLL is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * @dev: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * DFLL clock should be disabled by the CPUFreq driver. So, make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * sure it is disabled and disable all clocks needed by the DFLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) int tegra_dfll_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct tegra_dfll *td = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (dfll_is_running(td)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dev_err(td->dev, "DFLL still enabled while suspending\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) reset_control_assert(td->dvco_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) EXPORT_SYMBOL(tegra_dfll_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * tegra_dfll_resume - reinitialize DFLL on resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * @dev: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * DFLL is disabled and reset during suspend and resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * So, reinitialize the DFLL IP block back for use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * DFLL clock is enabled later in closed loop mode by CPUFreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * driver before switching its clock source to DFLL output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int tegra_dfll_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct tegra_dfll *td = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) reset_control_deassert(td->dvco_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) pm_runtime_get_sync(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dfll_set_mode(td, DFLL_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dfll_set_default_params(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (td->soc->init_clock_trimmers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) td->soc->init_clock_trimmers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dfll_set_open_loop_config(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dfll_init_out_if(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) pm_runtime_put_sync(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) EXPORT_SYMBOL(tegra_dfll_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * DT data fetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * Find a PMIC voltage register-to-voltage mapping for the given voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * An exact voltage match is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int i, n_voltages, reg_uV,reg_volt_id, align_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) align_step = uV / td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) n_voltages = regulator_count_voltages(td->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) for (i = 0; i < n_voltages; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) reg_uV = regulator_list_voltage(td->vdd_reg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (reg_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) reg_volt_id = reg_uV / td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (align_step == reg_volt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_err(td->dev, "no voltage map entry for %d uV\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * Find a PMIC voltage register-to-voltage mapping for the given voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * rounding up to the closest supported voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) int i, n_voltages, reg_uV, reg_volt_id, align_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) align_step = uV / td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) n_voltages = regulator_count_voltages(td->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) for (i = 0; i < n_voltages; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) reg_uV = regulator_list_voltage(td->vdd_reg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (reg_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) reg_volt_id = reg_uV / td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (align_step <= reg_volt_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * dfll_build_pwm_lut - build the PWM regulator lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * @v_max: Vmax from OPP table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * In this case closed loop output is controlling duty cycle directly. The s/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * look-up that maps PWM duty cycle to voltage is still built by this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) unsigned long rate, reg_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) u8 lut_bottom = MAX_DFLL_VOLTAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) int v_min = td->soc->cvb->min_millivolts * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) reg_volt = td->lut_uv[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* since opp voltage is exact mv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) reg_volt = (reg_volt / 1000) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (reg_volt > v_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) td->lut[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) lut_bottom = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* determine voltage boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) td->lut_size = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if ((lut_bottom == MAX_DFLL_VOLTAGES) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) (lut_bottom + 1 >= td->lut_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) td->soc->cvb->min_millivolts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) td->lut_bottom = lut_bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* determine rate boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) rate = get_dvco_rate_below(td, td->lut_bottom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) td->soc->cvb->min_millivolts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) td->dvco_rate_min = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * dfll_build_i2c_lut - build the I2C voltage register lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * @v_max: Vmax from OPP table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * PMIC voltage register values that span the entire DFLL operating range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * This function builds the look-up table based on the OPP table provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * register-to-voltage mapping queried from the regulator framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * On success, fills in td->lut and returns 0, or -err on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) unsigned long rate, v, v_opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) int j, selector, lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) v = td->soc->cvb->min_millivolts * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) lut = find_vdd_map_entry_exact(td, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (lut < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) td->lut[0] = lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) td->lut_bottom = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) for (j = 1, rate = 0; ; rate++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (IS_ERR(opp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) v_opp = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (v_opp <= td->soc->cvb->min_millivolts * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) td->dvco_rate_min = dev_pm_opp_get_freq(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (v >= v_opp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) selector = find_vdd_map_entry_min(td, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (selector < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (selector != td->lut[j - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) td->lut[j++] = selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) selector = find_vdd_map_entry_exact(td, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (selector < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (selector != td->lut[j - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) td->lut[j++] = selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (v >= v_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) td->lut_size = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (!td->dvco_rate_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) td->soc->cvb->min_millivolts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) for (j = 0; j < td->lut_size; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) td->lut_uv[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) regulator_list_voltage(td->vdd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) td->lut[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static int dfll_build_lut(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) unsigned long rate, v_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) rate = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) v_max = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return dfll_build_pwm_lut(td, v_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return dfll_build_i2c_lut(td, v_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * read_dt_param - helper function for reading required parameters from the DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * @param: DT property name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * @dest: output pointer for the value read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * Read a required numeric parameter from the DFLL device node, or complain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * if the property doesn't exist. Returns a boolean indicating success for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * easy chaining of multiple calls to this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) int err = of_property_read_u32(td->dev->of_node, param, dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dev_err(td->dev, "failed to read DT parameter %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) param, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * Read all the parameters required for operation in I2C mode. The parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) * can originate from the device tree or the regulator subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * Returns 0 on success or -err on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static int dfll_fetch_i2c_params(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) struct device *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) int vsel_reg, vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) regmap = regulator_get_regmap(td->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) i2c_dev = regmap_get_device(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) i2c_client = to_i2c_client(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) td->i2c_slave_addr = i2c_client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ret = regulator_get_hardware_vsel_register(td->vdd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) &vsel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) &vsel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) dev_err(td->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) "regulator unsuitable for DFLL I2C operation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) td->i2c_reg = vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static int dfll_fetch_pwm_params(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u32 pwm_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) dev_err(td->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) "Missing step or alignment info for PWM regulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) for (i = 0; i < MAX_DFLL_VOLTAGES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) td->lut_uv[i] = td->soc->alignment.offset_uv +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) i * td->soc->alignment.step_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) &td->reg_init_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) dev_err(td->dev, "couldn't get initialized voltage\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dev_err(td->dev, "couldn't get PWM period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) td->pwm_pin = devm_pinctrl_get(td->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (IS_ERR(td->pwm_pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) dev_err(td->dev, "DT: missing pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return PTR_ERR(td->pwm_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "dvfs_pwm_enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (IS_ERR(td->pwm_enable_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_err(td->dev, "DT: missing pwm enabled state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) return PTR_ERR(td->pwm_enable_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "dvfs_pwm_disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (IS_ERR(td->pwm_disable_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) dev_err(td->dev, "DT: missing pwm disabled state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return PTR_ERR(td->pwm_disable_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * dfll_fetch_common_params - read DFLL parameters from the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * @td: DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * Read all the DT parameters that are common to both I2C and PWM operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * Returns 0 on success or -EINVAL on any failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static int dfll_fetch_common_params(struct tegra_dfll *td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) bool ok = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ok &= read_dt_param(td, "nvidia,cf", &td->cf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) ok &= read_dt_param(td, "nvidia,ci", &td->ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ok &= read_dt_param(td, "nvidia,cg", &td->cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) td->cg_scale = of_property_read_bool(td->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) "nvidia,cg-scale");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (of_property_read_string(td->dev->of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) &td->output_clock_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) dev_err(td->dev, "missing clock-output-names property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) return ok ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * API exported to per-SoC platform drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * tegra_dfll_register - probe a Tegra DFLL device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) * @pdev: DFLL platform_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * @soc: Per-SoC integration and characterization data for this DFLL instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * Probe and initialize a DFLL device instance. Intended to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * by a SoC-specific shim driver that passes in per-SoC integration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * and configuration data via @soc. Returns 0 on success or -err on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) int tegra_dfll_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct tegra_dfll_soc_data *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) struct tegra_dfll *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (!soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (!td)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) td->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) platform_set_drvdata(pdev, td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) td->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (IS_ERR(td->dvco_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev_err(td->dev, "couldn't get dvco reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return PTR_ERR(td->dvco_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ret = dfll_fetch_common_params(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) dev_err(td->dev, "couldn't parse device tree parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) td->pmu_if = TEGRA_DFLL_PMU_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ret = dfll_fetch_pwm_params(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (IS_ERR(td->vdd_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return PTR_ERR(td->vdd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) td->pmu_if = TEGRA_DFLL_PMU_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ret = dfll_fetch_i2c_params(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret = dfll_build_lut(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) dev_err(td->dev, "couldn't build LUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_err(td->dev, "no control register resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (!td->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) dev_err(td->dev, "couldn't ioremap DFLL control registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) dev_err(td->dev, "no i2c_base resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (!td->i2c_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) dev_err(td->dev, "couldn't ioremap i2c_base resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) mem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) dev_err(td->dev, "no i2c_controller_base resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) td->i2c_controller_base = devm_ioremap(td->dev, mem->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (!td->i2c_controller_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) dev_err(td->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) "couldn't ioremap i2c_controller_base resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) mem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) dev_err(td->dev, "no lut_base resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (!td->lut_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) dev_err(td->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) "couldn't ioremap lut_base resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ret = dfll_init_clks(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) dev_err(&pdev->dev, "DFLL clock init error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* Enable the clocks and set the device up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ret = dfll_init(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ret = dfll_register_clk(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) dev_err(&pdev->dev, "DFLL clk registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dfll_debug_init(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) EXPORT_SYMBOL(tegra_dfll_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) * tegra_dfll_unregister - release all of the DFLL driver resources for a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * @pdev: DFLL platform_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * Unbind this driver from the DFLL hardware device represented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * @pdev. The DFLL must be disabled for this to succeed. Returns a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * soc pointer upon success or -EBUSY if the DFLL is still active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct tegra_dfll *td = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* Try to prevent removal while the DFLL is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (td->mode != DFLL_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) "must disable DFLL before removing driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) debugfs_remove_recursive(td->debugfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) dfll_unregister_clk(td);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) clk_unprepare(td->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) clk_unprepare(td->soc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) clk_unprepare(td->i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) reset_control_assert(td->dvco_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) return td->soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) EXPORT_SYMBOL(tegra_dfll_unregister);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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