Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 						 unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	return sync->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				       unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	if (rate > sync->max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int clk_sync_source_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 				    unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	sync->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const struct clk_ops tegra_clk_sync_source_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	.round_rate = clk_sync_source_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	.set_rate = clk_sync_source_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	.recalc_rate = clk_sync_source_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *tegra_clk_register_sync_source(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 					   unsigned long max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct tegra_clk_sync_source *sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	sync = kzalloc(sizeof(*sync), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (!sync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		pr_err("%s: could not allocate sync source clk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	sync->max_rate = max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	init.ops = &tegra_clk_sync_source_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	/* Data in .init is copied by clk_register(), so stack variable OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	sync->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	clk = clk_register(NULL, &sync->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		kfree(sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }