^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Allwinner A80 CPUS clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static DEFINE_SPINLOCK(sun9i_a80_cpus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUN9I_CPUS_MAX_PARENTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUN9I_CPUS_MUX_PARENT_PLL4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUN9I_CPUS_MUX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN9I_CPUS_MUX_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN9I_CPUS_MUX_GET_PARENT(reg) ((reg & SUN9I_CPUS_MUX_MASK) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SUN9I_CPUS_MUX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN9I_CPUS_DIV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN9I_CPUS_DIV_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN9I_CPUS_DIV_GET(reg) ((reg & SUN9I_CPUS_DIV_MASK) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SUN9I_CPUS_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (div << SUN9I_CPUS_DIV_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUN9I_CPUS_PLL4_DIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUN9I_CPUS_PLL4_DIV_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUN9I_CPUS_PLL4_DIV_GET(reg) ((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SUN9I_CPUS_PLL4_DIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct sun9i_a80_cpus_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define to_sun9i_a80_cpus_clk(_hw) container_of(_hw, struct sun9i_a80_cpus_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static unsigned long sun9i_a80_cpus_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Fetch the register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg = readl(cpus->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* apply pre-divider first if parent is pll4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* clk divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 parent, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 div, pre_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * clock can only divide, so we will never be able to achieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * frequencies higher than the parent frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (parent_rate && rate > parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) div = DIV_ROUND_UP(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* calculate pre-divider if parent is pll4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* pre-divider is 1 ~ 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (div < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pre_div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else if (div < 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pre_div = DIV_ROUND_UP(div, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } else if (div < 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pre_div = DIV_ROUND_UP(div, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pre_div = DIV_ROUND_UP(div, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* we were asked to pass back divider values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (divp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *divp = div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *pre_divp = pre_div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return parent_rate / pre_div / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int sun9i_a80_cpus_clk_determine_rate(struct clk_hw *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk_hw *parent, *best_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int i, num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long rate = req->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* find the parent that can help provide the fastest rate <= rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) num_parents = clk_hw_get_num_parents(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) parent = clk_hw_get_parent_by_index(clk, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (clk_hw_get_flags(clk) & CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) parent_rate = clk_hw_round_rate(parent, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) child_rate = sun9i_a80_cpus_clk_round(rate, NULL, NULL, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (child_rate <= rate && child_rate > best_child_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) best_parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) best = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) best_child_rate = child_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!best_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) req->best_parent_hw = best_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) req->best_parent_rate = best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) req->rate = best_child_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int sun9i_a80_cpus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 div, pre_div, parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spin_lock_irqsave(&sun9i_a80_cpus_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reg = readl(cpus->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* need to know which parent is used to apply pre-divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) parent = SUN9I_CPUS_MUX_GET_PARENT(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) reg = SUN9I_CPUS_DIV_SET(reg, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(reg, cpus->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) spin_unlock_irqrestore(&sun9i_a80_cpus_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct clk_ops sun9i_a80_cpus_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .determine_rate = sun9i_a80_cpus_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .recalc_rate = sun9i_a80_cpus_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .set_rate = sun9i_a80_cpus_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void sun9i_a80_cpus_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const char *parents[SUN9I_CPUS_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct sun9i_a80_cpus_clk *cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cpus = kzalloc(sizeof(*cpus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cpus->reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (IS_ERR(cpus->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto err_free_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* we have a mux, we will have >1 parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = of_clk_parent_fill(node, parents, SUN9I_CPUS_MAX_PARENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* set up clock properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mux->reg = cpus->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mux->shift = SUN9I_CPUS_MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* un-shifted mask is what mux_clk expects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mux->mask = SUN9I_CPUS_MUX_MASK >> SUN9I_CPUS_MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mux->lock = &sun9i_a80_cpus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk = clk_register_composite(NULL, clk_name, parents, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &mux->hw, &clk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) &cpus->hw, &sun9i_a80_cpus_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) NULL, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto err_free_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto err_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err_free_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) iounmap(cpus->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) release_mem_region(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err_free_cpus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) kfree(cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CLK_OF_DECLARE(sun9i_a80_cpus, "allwinner,sun9i-a80-cpus-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) sun9i_a80_cpus_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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