Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Allwinner A31 APB0 clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * The APB0 clk has a configurable divisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * We must use a clk_div_table and not a regular power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * divisor here, because the first 2 values divide the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * by 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct clk_div_table sun6i_a31_apb0_divs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	{ .val = 0, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{ .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{ .val = 2, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{ .val = 3, .div = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	const char *clk_name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	const char *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	reg = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clk_parent = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	if (!clk_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	of_property_read_string(np, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 					 0, reg, 0, 2, 0, sun6i_a31_apb0_divs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 					 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	{ .compatible = "allwinner,sun6i-a31-apb0-clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct platform_driver sun6i_a31_apb0_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		.name = "sun6i-a31-apb0-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		.of_match_table = sun6i_a31_apb0_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	.probe = sun6i_a31_apb0_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) builtin_platform_driver(sun6i_a31_apb0_clk_driver);