^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SUN4I_A10_PLL3_GATE_BIT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SUN4I_A10_PLL3_DIV_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SUN4I_A10_PLL3_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void __init sun4i_a10_pll3_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) const char *clk_name = node->name, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_multiplier *mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) parent = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pr_err("%s: Could not map the clock registers\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) gate->lock = &sun4i_a10_pll3_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mult = kzalloc(sizeof(*mult), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) goto err_free_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mult->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mult->lock = &sun4i_a10_pll3_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk = clk_register_composite(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) &parent, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) &mult->hw, &clk_multiplier_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) &gate->hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_err("%s: Couldn't register the clock\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) goto err_free_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pr_err("%s: Couldn't register DT provider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) goto err_clk_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) err_clk_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clk_unregister_composite(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) err_free_mult:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) kfree(mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err_free_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) release_mem_region(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) sun4i_a10_pll3_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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