Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2015 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct sun4i_a10_display_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	bool	has_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	u8	num_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u8	parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u8	offset_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u8	offset_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u8	offset_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u8	offset_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u8	width_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u8	width_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void __iomem			*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	spinlock_t			*lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct reset_controller_dev	rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u8				offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static DEFINE_SPINLOCK(sun4i_a10_display_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static inline struct reset_data *rcdev_to_reset_data(struct reset_controller_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return container_of(rcdev, struct reset_data, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 				    unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct reset_data *data = rcdev_to_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spin_lock_irqsave(data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	reg = readl(data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	writel(reg & ~BIT(data->offset + id), data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	spin_unlock_irqrestore(data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 				      unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct reset_data *data = rcdev_to_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	spin_lock_irqsave(data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	reg = readl(data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	writel(reg | BIT(data->offset + id), data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	spin_unlock_irqrestore(data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				    unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct reset_data *data = rcdev_to_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return !(readl(data->reg) & BIT(data->offset + id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static const struct reset_control_ops sun4i_a10_display_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.assert		= sun4i_a10_display_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.deassert	= sun4i_a10_display_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.status		= sun4i_a10_display_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int sun4i_a10_display_reset_xlate(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 					 const struct of_phandle_args *spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* We only have a single reset signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void __init sun4i_a10_display_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					  const struct sun4i_a10_display_clk_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	const char *parents[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct reset_data *reset_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct clk_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		pr_err("%s: Could not map the clock registers\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ret = of_clk_parent_fill(node, parents, data->parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (ret != data->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		pr_err("%s: Could not retrieve the parents\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mux->shift = data->offset_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	mux->mask = (1 << data->width_mux) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mux->lock = &sun4i_a10_display_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		goto free_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	gate->bit_idx = data->offset_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	gate->lock = &sun4i_a10_display_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (data->has_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			goto free_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		div->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		div->shift = data->offset_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		div->width = data->width_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		div->lock = &sun4i_a10_display_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	clk = clk_register_composite(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				     parents, data->parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				     &mux->hw, &clk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				     data->has_div ? &div->hw : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				     data->has_div ? &clk_divider_ops : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				     &gate->hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				     data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		pr_err("%s: Couldn't register the clock\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		goto free_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		pr_err("%s: Couldn't register DT provider\n", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (!data->num_rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!reset_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		goto free_of_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	reset_data->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	reset_data->offset = data->offset_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	reset_data->lock = &sun4i_a10_display_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	reset_data->rcdev.nr_resets = data->num_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	reset_data->rcdev.ops = &sun4i_a10_display_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	reset_data->rcdev.of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (data->num_rst == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		reset_data->rcdev.of_reset_n_cells = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		reset_data->rcdev.of_xlate = &sun4i_a10_display_reset_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		reset_data->rcdev.of_reset_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (reset_controller_register(&reset_data->rcdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		pr_err("%s: Couldn't register the reset controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		       clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		goto free_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) free_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	kfree(reset_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) free_of_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	of_clk_del_provider(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	clk_unregister_composite(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) free_div:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) free_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) free_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	release_mem_region(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct sun4i_a10_display_clk_data sun4i_a10_tcon_ch0_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.num_rst	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.parents	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.offset_en	= 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.offset_rst	= 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.offset_mux	= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.width_mux	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.flags		= CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void __init sun4i_a10_tcon_ch0_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	sun4i_a10_display_init(node, &sun4i_a10_tcon_ch0_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CLK_OF_DECLARE(sun4i_a10_tcon_ch0, "allwinner,sun4i-a10-tcon-ch0-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	       sun4i_a10_tcon_ch0_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct sun4i_a10_display_clk_data sun4i_a10_display_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.has_div	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.num_rst	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.parents	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.offset_en	= 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.offset_rst	= 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.offset_mux	= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.offset_div	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.width_mux	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.width_div	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void __init sun4i_a10_display_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	sun4i_a10_display_init(node, &sun4i_a10_display_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CLK_OF_DECLARE(sun4i_a10_display, "allwinner,sun4i-a10-display-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	       sun4i_a10_display_setup);