^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013 Emilio López
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Emilio López <emilio@elopez.com.ar>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk-factors.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * MOD0 rate is calculated as follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * rate = (parent_rate >> p) / (m + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void sun4i_a10_get_mod0_factors(struct factors_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 div, calcm, calcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* These clocks can only divide, so we will never be able to achieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * frequencies higher than the parent frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (req->rate > req->parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) req->rate = req->parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) div = DIV_ROUND_UP(req->parent_rate, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (div < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) calcp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) else if (div / 2 < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) calcp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) else if (div / 4 < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) calcp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) calcp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) calcm = DIV_ROUND_UP(div, 1 << calcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) req->rate = (req->parent_rate >> calcp) / calcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) req->m = calcm - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) req->p = calcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* user manual says "n" but it's really "p" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct clk_factors_config sun4i_a10_mod0_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .mshift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .mwidth = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .pshift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pwidth = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct factors_data sun4i_a10_mod0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .enable = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mux = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .muxmask = BIT(1) | BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .table = &sun4i_a10_mod0_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .getter = sun4i_a10_get_mod0_factors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void __init sun4i_a10_mod0_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * This happens with mod0 clk nodes instantiated through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * mfd, as those do not have their resources assigned at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * CLK_OF_DECLARE time yet, so do not print an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) sunxi_factors_register(node, &sun4i_a10_mod0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &sun4i_a10_mod0_lock, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_OF_DECLARE_DRIVER(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) sun4i_a10_mod0_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sunxi_factors_register(np, &sun4i_a10_mod0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &sun4i_a10_mod0_lock, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { .compatible = "allwinner,sun4i-a10-mod0-clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct platform_driver sun4i_a10_mod0_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "sun4i-a10-mod0-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .of_match_table = sun4i_a10_mod0_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .probe = sun4i_a10_mod0_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) builtin_platform_driver(sun4i_a10_mod0_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct factors_data sun9i_a80_mod0_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .enable = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mux = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .table = &sun4i_a10_mod0_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .getter = sun4i_a10_get_mod0_factors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void __init sun9i_a80_mod0_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_err("Could not get registers for mod0-clk: %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sunxi_factors_register(node, &sun9i_a80_mod0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &sun4i_a10_mod0_lock, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void __init sun5i_a13_mbus_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pr_err("Could not get registers for a13-mbus-clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* The MBUS clocks needs to be always enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sunxi_factors_register_critical(node, &sun4i_a10_mod0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) &sun5i_a13_mbus_lock, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mmc_phase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int mmc_get_phase(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct clk *mmc, *mmc_parent, *clk = hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct mmc_phase *phase = to_mmc_phase(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int mmc_rate, mmc_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 step, mmc_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) value = readl(phase->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) delay = (value >> phase->offset) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Get the main MMC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mmc = clk_get_parent(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* And its rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mmc_rate = clk_get_rate(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!mmc_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Now, get the MMC parent (most likely some PLL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mmc_parent = clk_get_parent(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!mmc_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* And its rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mmc_parent_rate = clk_get_rate(mmc_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!mmc_parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Get MMC clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mmc_div = mmc_parent_rate / mmc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) step = DIV_ROUND_CLOSEST(360, mmc_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return delay * step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int mmc_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct clk *mmc, *mmc_parent, *clk = hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct mmc_phase *phase = to_mmc_phase(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int mmc_rate, mmc_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Get the main MMC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mmc = clk_get_parent(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* And its rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mmc_rate = clk_get_rate(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!mmc_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Now, get the MMC parent (most likely some PLL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mmc_parent = clk_get_parent(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!mmc_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* And its rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mmc_parent_rate = clk_get_rate(mmc_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!mmc_parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (degrees != 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u16 step, mmc_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Get MMC clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mmc_div = mmc_parent_rate / mmc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * We can only outphase the clocks by multiple of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * PLL's period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Since the MMC clock in only a divider, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * formula to get the outphasing in degrees is deg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * 360 * delta / period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * If we simplify this formula, we can see that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * only thing that we're concerned about is the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * of period we want to outphase our clock from, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * the divider set by the MMC clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) step = DIV_ROUND_CLOSEST(360, mmc_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) delay = DIV_ROUND_CLOSEST(degrees, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_lock_irqsave(phase->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) value = readl(phase->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) value &= ~GENMASK(phase->offset + 3, phase->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) value |= delay << phase->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel(value, phase->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_unlock_irqrestore(phase->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct clk_ops mmc_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .get_phase = mmc_get_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .set_phase = mmc_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * sunxi_mmc_setup - Common setup function for mmc module clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * The only difference between module clocks on different platforms is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * width of the mux register bits and the valid values, which are passed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * through struct factors_data. The phase clocks parts are identical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void __init sunxi_mmc_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct factors_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_err("Couldn't map the %pOFn clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!clk_data->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto err_free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) clk_data->clk_num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!clk_data->clks[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto err_free_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) parent = __clk_get_name(clk_data->clks[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) for (i = 1; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .parent_names = &parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .ops = &mmc_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct mmc_phase *phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) phase = kmalloc(sizeof(*phase), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) phase->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) phase->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) phase->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (i == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) phase->offset = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) phase->offset = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) i, &init.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) init.name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk_data->clks[i] = clk_register(NULL, &phase->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (IS_ERR(clk_data->clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) kfree(phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err_free_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) kfree(clk_data->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) err_free_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void __init sun4i_a10_mmc_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void __init sun9i_a80_mmc_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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