^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Adjustable factor-based clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-factors.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * DOC: basic adjustable factor-based clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * prepare - clk_prepare only ensures that parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * enable - clk_enable only ensures that parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * rate - rate is adjustable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FACTORS_MAX_PARENTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLRMASK(len, pos) (~(SETMASK(len, pos)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FACTOR_SET(bit, len, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) (((reg) & CLRMASK(len, bit)) | (val << (bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 n = 1, k = 0, p = 0, m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_factors *factors = to_clk_factors(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const struct clk_factors_config *config = factors->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Fetch the register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg = readl(factors->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Get each individual factor if applicable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) n = FACTOR_GET(config->nshift, config->nwidth, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) k = FACTOR_GET(config->kshift, config->kwidth, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) m = FACTOR_GET(config->mshift, config->mwidth, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) p = FACTOR_GET(config->pshift, config->pwidth, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (factors->recalc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct factors_request factors_req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .parent_rate = parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .n = n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .k = k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .m = m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .p = p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* get mux details from mux clk structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (factors->mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) factors_req.parent_index =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (reg >> factors->mux->shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) factors->mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) factors->recalc(&factors_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return factors_req.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Calculate the rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int clk_factors_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct clk_factors *factors = to_clk_factors(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_hw *parent, *best_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int i, num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* find the parent that can help provide the fastest rate <= rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) num_parents = clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct factors_request factors_req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .rate = req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .parent_index = i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) parent = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) parent_rate = clk_hw_round_rate(parent, req->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) factors_req.parent_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) factors->get_factors(&factors_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) child_rate = factors_req.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (child_rate <= req->rate && child_rate > best_child_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) best_parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) best = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) best_child_rate = child_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!best_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) req->best_parent_hw = best_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) req->best_parent_rate = best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) req->rate = best_child_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct factors_request req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .rate = rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .parent_rate = parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_factors *factors = to_clk_factors(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct clk_factors_config *config = factors->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) factors->get_factors(&req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (factors->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_lock_irqsave(factors->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Fetch the register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg = readl(factors->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Set up the new factors - macros do not do anything if width is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Apply them now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(reg, factors->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* delay 500us so pll stabilizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __delay((rate >> 20) * 500 / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (factors->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_unlock_irqrestore(factors->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct clk_ops clk_factors_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .determine_rate = clk_factors_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .recalc_rate = clk_factors_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_rate = clk_factors_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clk *__sunxi_factors_register(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct factors_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) spinlock_t *lock, void __iomem *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk_factors *factors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct clk_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clk_hw *gate_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk_hw *mux_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const char *parents[FACTORS_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* if we have a mux, we will have >1 parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * some factor clocks, such as pll5 and pll6, may have multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * outputs, and have their name designated in factors_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (data->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_name = data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!factors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto err_factors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* set up factors properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) factors->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) factors->config = data->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) factors->get_factors = data->getter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) factors->recalc = data->recalc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) factors->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Add a gate if this factor clock can be gated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (data->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto err_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) factors->gate = gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* set up gate properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) gate->bit_idx = data->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) gate->lock = factors->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Add a mux if this factor clock can be muxed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (data->mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) factors->mux = mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* set up gate properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mux->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mux->shift = data->mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mux->mask = data->muxmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mux->lock = factors->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk = clk_register_composite(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) parents, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mux_hw, &clk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &factors->hw, &clk_factors_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) gate_hw, &clk_gate_ops, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto err_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err_provider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* TODO: The composite clock stuff will leak a bit here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) err_mux:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) kfree(factors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err_factors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct clk *sunxi_factors_register(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) const struct factors_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return __sunxi_factors_register(node, data, lock, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct clk *sunxi_factors_register_critical(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct factors_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct clk_hw *hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct clk_factors *factors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) factors = to_clk_factors(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) of_clk_del_provider(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* TODO: The composite clock stuff will leak a bit here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) kfree(factors->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) kfree(factors->gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) kfree(factors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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