^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013 Emilio López
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Emilio López <emilio@elopez.com.ar>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2015 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/sun4i-a10-pll2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SUN4I_PLL2_ENABLE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SUN4I_PLL2_PRE_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SUN4I_PLL2_PRE_DIV_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUN4I_PLL2_N_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUN4I_PLL2_N_WIDTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUN4I_PLL2_POST_DIV_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUN4I_PLL2_POST_DIV_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN4I_PLL2_POST_DIV_VALUE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUN4I_PLL2_OUTPUTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void __init sun4i_pll2_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int post_div_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *clk_name = node->name, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk **clks, *base_clk, *prediv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clk_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk_multiplier *mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) goto err_free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) parent = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) prediv_clk = clk_register_divider(NULL, "pll2-prediv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) parent, 0, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SUN4I_PLL2_PRE_DIV_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SUN4I_PLL2_PRE_DIV_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) &sun4i_a10_pll2_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (IS_ERR(prediv_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_err("Couldn't register the prediv clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto err_free_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Setup the gate part of the PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) goto err_unregister_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) gate->bit_idx = SUN4I_PLL2_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) gate->lock = &sun4i_a10_pll2_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Setup the multiplier part of the PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto err_free_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mult->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mult->shift = SUN4I_PLL2_N_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mult->width = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_MULTIPLIER_ROUND_CLOSEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mult->lock = &sun4i_a10_pll2_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) parent = __clk_get_name(prediv_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) base_clk = clk_register_composite(NULL, "pll2-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &parent, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) &mult->hw, &clk_multiplier_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &gate->hw, &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (IS_ERR(base_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pr_err("Couldn't register the base multiplier clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) goto err_free_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) parent = __clk_get_name(base_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * PLL2-1x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * This is supposed to have a post divider, but we won't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * to use it, we just need to initialise it to 4, and use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * fixed divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SUN4I_A10_PLL2_1X, &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SUN4I_PLL2_POST_DIV_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * PLL2-2x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * This clock doesn't use the post divider, and really is just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * a fixed divider from the PLL2 base clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SUN4I_A10_PLL2_2X, &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* PLL2-4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SUN4I_A10_PLL2_4X, &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* PLL2-8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SUN4I_A10_PLL2_8X, &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk_data->clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err_free_multiplier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) kfree(mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err_free_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err_unregister_prediv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clk_unregister_divider(prediv_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err_free_array:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) kfree(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) err_free_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void __init sun4i_a10_pll2_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sun4i_pll2_setup(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sun4i_a10_pll2_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __init sun5i_a13_pll2_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sun4i_pll2_setup(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sun5i_a13_pll2_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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