Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _CCU_SDM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _CCU_SDM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct ccu_sdm_setting {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	unsigned long	rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 * XXX We don't know what the step and bottom register fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 * mean. Just copy the whole register value from the vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	 * kernel for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u32		pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 * M and N factors here should be the values used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	 * calculation, not the raw values written to registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u32		m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u32		n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct ccu_sdm_internal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct ccu_sdm_setting	*table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u32		table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* early SoCs don't have the SDM enable bit in the PLL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u32		enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/* second enable bit in tuning register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u32		tuning_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u16		tuning_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define _SUNXI_CCU_SDM(_table, _enable,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		       _reg, _reg_enable)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		.table		= _table,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		.table_size	= ARRAY_SIZE(_table),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.enable		= _enable,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		.tuning_enable	= _reg_enable,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		.tuning_reg	= _reg,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			       struct ccu_sdm_internal *sdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void ccu_sdm_helper_enable(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			   struct ccu_sdm_internal *sdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			   unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void ccu_sdm_helper_disable(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			    struct ccu_sdm_internal *sdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bool ccu_sdm_helper_has_rate(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			     struct ccu_sdm_internal *sdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			     unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 				       struct ccu_sdm_internal *sdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 				       u32 m, u32 n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int ccu_sdm_helper_get_factors(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			       struct ccu_sdm_internal *sdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			       unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			       unsigned long *m, unsigned long *n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif