Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _CCU_NKM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _CCU_NKM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * struct ccu_nkm - Definition of an N-K-M clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * Clocks based on the formula parent * N * K / M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct ccu_nkm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u32			enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u32			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct ccu_mult_internal	n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct ccu_mult_internal	k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	struct ccu_div_internal		m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	struct ccu_mux_internal	mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned int		fixed_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct ccu_common	common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 					 _nshift, _nwidth,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 					 _kshift, _kwidth,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 					 _mshift, _mwidth,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 					 _muxshift, _muxwidth,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 					 _gate, _lock, _flags)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct ccu_nkm _struct = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		.enable		= _gate,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		.lock		= _lock,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		.k		= _SUNXI_CCU_MULT(_kshift, _kwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.mux		= _SUNXI_CCU_MUX(_muxshift, _muxwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		.common		= {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			.reg		= _reg,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			.hw.init	= CLK_HW_INIT_PARENTS(_name,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 						      _parents,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 						      &ccu_nkm_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 						      _flags),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				     _nshift, _nwidth,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 				     _kshift, _kwidth,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				     _mshift, _mwidth,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 				     _gate, _lock, _flags)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	struct ccu_nkm _struct = {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		.enable		= _gate,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		.lock		= _lock,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		.k		= _SUNXI_CCU_MULT(_kshift, _kwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		.common		= {					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			.reg		= _reg,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			.hw.init	= CLK_HW_INIT(_name,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 						      _parent,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 						      &ccu_nkm_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 						      _flags),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline struct ccu_nkm *hw_to_ccu_nkm(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	struct ccu_common *common = hw_to_ccu_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	return container_of(common, struct ccu_nkm, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern const struct clk_ops ccu_nkm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif /* _CCU_NKM_H_ */