Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ccu_mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static u16 ccu_mux_get_prediv(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 			      struct ccu_mux_internal *cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 			      int parent_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u16 prediv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	      (common->features & CCU_FEATURE_VARIABLE_PREDIV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	      (common->features & CCU_FEATURE_ALL_PREDIV)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	if (common->features & CCU_FEATURE_ALL_PREDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		return common->prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	reg = readl(common->base + common->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (parent_index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		parent_index = reg >> cm->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		parent_index &= (1 << cm->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	if (common->features & CCU_FEATURE_FIXED_PREDIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		for (i = 0; i < cm->n_predivs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			if (parent_index == cm->fixed_predivs[i].index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 				prediv = cm->fixed_predivs[i].div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (common->features & CCU_FEATURE_VARIABLE_PREDIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		for (i = 0; i < cm->n_var_predivs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			if (parent_index == cm->var_predivs[i].index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 				div = reg >> cm->var_predivs[i].shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				div &= (1 << cm->var_predivs[i].width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				prediv = div + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 					  struct ccu_mux_internal *cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 					  int parent_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 					  unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					    struct ccu_mux_internal *cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					    int parent_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 					    unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return parent_rate * ccu_mux_get_prediv(common, cm, parent_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) int ccu_mux_helper_determine_rate(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 				  struct ccu_mux_internal *cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				  struct clk_rate_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				  unsigned long (*round)(struct ccu_mux_internal *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 							 struct clk_hw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 							 unsigned long *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 							 unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 							 void *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				  void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned long best_parent_rate = 0, best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct clk_hw *best_parent, *hw = &common->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		unsigned long adj_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		best_parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		best_parent_rate = clk_hw_get_rate(best_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		adj_parent_rate = ccu_mux_helper_apply_prediv(common, cm, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 							      best_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		best_rate = round(cm, best_parent, &adj_parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				  req->rate, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 * adj_parent_rate might have been modified by our clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		 * Unapply the pre-divider if there's one, and give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		 * the actual frequency the parent needs to run at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 								 adj_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		unsigned long tmp_rate, parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		parent = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		parent_rate = ccu_mux_helper_apply_prediv(common, cm, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 							  clk_hw_get_rate(parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		tmp_rate = round(cm, parent, &parent_rate, req->rate, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		 * parent_rate might have been modified by our clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		 * Unapply the pre-divider if there's one, and give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		 * the actual frequency the parent needs to run at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		parent_rate = ccu_mux_helper_unapply_prediv(common, cm, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 							    parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (tmp_rate == req->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			best_parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			best_parent_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		if ((req->rate - tmp_rate) < (req->rate - best_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			best_parent_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			best_parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (best_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	req->best_parent_hw = best_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	req->best_parent_rate = best_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	req->rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 ccu_mux_helper_get_parent(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			     struct ccu_mux_internal *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u8 parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	reg = readl(common->base + common->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	parent = reg >> cm->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	parent &= (1 << cm->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (cm->table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		int num_parents = clk_hw_get_num_parents(&common->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		for (i = 0; i < num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			if (cm->table[i] == parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ccu_mux_helper_set_parent(struct ccu_common *common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			      struct ccu_mux_internal *cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			      u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (cm->table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		index = cm->table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	spin_lock_irqsave(common->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	reg = readl(common->base + common->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	writel(reg | (index << cm->shift), common->base + common->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	spin_unlock_irqrestore(common->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void ccu_mux_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct ccu_mux *cm = hw_to_ccu_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return ccu_gate_helper_disable(&cm->common, cm->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int ccu_mux_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct ccu_mux *cm = hw_to_ccu_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return ccu_gate_helper_enable(&cm->common, cm->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ccu_mux_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct ccu_mux *cm = hw_to_ccu_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static u8 ccu_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct ccu_mux *cm = hw_to_ccu_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct ccu_mux *cm = hw_to_ccu_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					 unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct ccu_mux *cm = hw_to_ccu_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					   parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const struct clk_ops ccu_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.disable	= ccu_mux_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.enable		= ccu_mux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.is_enabled	= ccu_mux_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.get_parent	= ccu_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.set_parent	= ccu_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.determine_rate	= __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.recalc_rate	= ccu_mux_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * This clock notifier is called when the frequency of the of the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * PLL clock is to be changed. The idea is to switch the parent to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * stable clock, such as the main oscillator, while the PLL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * stabilizes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int ccu_mux_notifier_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			       unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct ccu_mux_nb *mux = to_ccu_mux_nb(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (event == PRE_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		mux->original_index = ccu_mux_helper_get_parent(mux->common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 								mux->cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 						mux->bypass_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	} else if (event == POST_RATE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 						mux->original_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	udelay(mux->delay_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return clk_notifier_register(clk, &mux_nb->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }