^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _CCU_MP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _CCU_MP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_mux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * struct ccu_mp - Definition of an M-P clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Clocks based on the formula parent >> P / M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct ccu_mp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ccu_div_internal m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct ccu_div_internal p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct ccu_mux_internal mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int fixed_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct ccu_common common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) _mshift, _mwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) _pshift, _pwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) _muxshift, _muxwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) _gate, _postdiv, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ccu_mp _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .enable = _gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .fixed_post_div = _postdiv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .features = CCU_FEATURE_FIXED_POSTDIV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .hw.init = CLK_HW_INIT_PARENTS(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &ccu_mp_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) _mshift, _mwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) _pshift, _pwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) _muxshift, _muxwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) _gate, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ccu_mp _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .enable = _gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .p = _SUNXI_CCU_DIV(_pshift, _pwidth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .hw.init = CLK_HW_INIT_PARENTS(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) &ccu_mp_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) _mshift, _mwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) _pshift, _pwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) _muxshift, _muxwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) _mshift, _mwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) _pshift, _pwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) _muxshift, _muxwidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0, _flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct ccu_common *common = hw_to_ccu_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return container_of(common, struct ccu_mp, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern const struct clk_ops ccu_mp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Special class of M-P clock that supports MMC timing modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Since the MMC clock registers all follow the same layout, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * simplify the macro for this particular case. In addition, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * switching modes also affects the output clock rate, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * have CLK_GET_RATE_NOCACHE for all these types of clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ccu_mp _struct = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .enable = BIT(31), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .m = _SUNXI_CCU_DIV(0, 4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .p = _SUNXI_CCU_DIV(16, 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .mux = _SUNXI_CCU_MUX(24, 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .common = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .features = CCU_FEATURE_MMC_TIMING_SWITCH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .hw.init = CLK_HW_INIT_PARENTS(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) &ccu_mp_mmc_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CLK_GET_RATE_NOCACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern const struct clk_ops ccu_mp_mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif /* _CCU_MP_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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