Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 			     unsigned int max_m, unsigned int max_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 			     unsigned int *m, unsigned int *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	unsigned long best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	unsigned int best_m = 0, best_p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	unsigned int _m, _p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	for (_p = 1; _p <= max_p; _p <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		for (_m = 1; _m <= max_m; _m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			unsigned long tmp_rate = parent / _p / _m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			if (tmp_rate > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			if ((rate - tmp_rate) < (rate - best_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 				best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 				best_m = _m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 				best_p = _p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	*m = best_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	*p = best_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 						      unsigned long *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 						      unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 						      unsigned int max_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 						      unsigned int max_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned long parent_rate_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned long parent_rate, now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned long best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int _m, _p, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned long maxdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	parent_rate_saved = *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * The maximum divider we can use without overflowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * unsigned long in rate * m * p below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	maxdiv = max_m * max_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	maxdiv = min(ULONG_MAX / rate, maxdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	for (_p = 1; _p <= max_p; _p <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		for (_m = 1; _m <= max_m; _m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			div = _m * _p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			if (div > maxdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			if (rate * div == parent_rate_saved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				 * It's the most ideal case if the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				 * rate can be divided from parent clock without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				 * needing to change parent rate, so return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				 * divider immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				*parent = parent_rate_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			parent_rate = clk_hw_round_rate(hw, rate * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			now = parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			if (now <= rate && now > best_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				best_rate = now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				*parent = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				if (now == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				       struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				       unsigned long *parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				       unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				       void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct ccu_mp *cmp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int max_m, max_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned int m, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		rate *= cmp->fixed_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	max_m = cmp->m.max ?: 1 << cmp->m.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		rate = *parent_rate / p / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 							max_m, max_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		rate /= cmp->fixed_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void ccu_mp_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return ccu_gate_helper_disable(&cmp->common, cmp->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int ccu_mp_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ccu_gate_helper_enable(&cmp->common, cmp->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ccu_mp_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned int m, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Adjust parent_rate according to pre-dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 						  parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	reg = readl(cmp->common.base + cmp->common.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	m = reg >> cmp->m.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	m &= (1 << cmp->m.width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	m += cmp->m.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (!m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		m++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	p = reg >> cmp->p.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	p &= (1 << cmp->p.width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	rate = (parent_rate >> p) / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		rate /= cmp->fixed_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ccu_mp_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				 struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 					     req, ccu_mp_round_rate, cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			   unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned int max_m, max_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned int m, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Adjust parent_rate according to pre-dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 						  parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	max_m = cmp->m.max ?: 1 << cmp->m.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* Adjust target rate according to post-dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		rate = rate * cmp->fixed_post_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	spin_lock_irqsave(cmp->common.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	reg = readl(cmp->common.base + cmp->common.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	reg |= (m - cmp->m.offset) << cmp->m.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	reg |= ilog2(p) << cmp->p.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	writel(reg, cmp->common.base + cmp->common.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	spin_unlock_irqrestore(cmp->common.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static u8 ccu_mp_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct ccu_mp *cmp = hw_to_ccu_mp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct clk_ops ccu_mp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.disable	= ccu_mp_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.enable		= ccu_mp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.is_enabled	= ccu_mp_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.get_parent	= ccu_mp_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.set_parent	= ccu_mp_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.determine_rate	= ccu_mp_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.recalc_rate	= ccu_mp_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.set_rate	= ccu_mp_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * Support for MMC timing mode switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * The MMC clocks on some SoCs support switching between old and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * new timing modes. A platform specific API is provided to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * and set the timing mode on supported SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * In addition, a special class of ccu_mp_ops is provided, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * takes in to account the timing mode switch. When the new timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * mode is active, the clock output rate is halved. This new class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * is a wrapper around the generic ccu_mp_ops. When clock rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * are passed through to ccu_mp_ops callbacks, they are doubled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * if the new timing mode bit is set, to account for the post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * divider. Conversely, when clock rates are passed back, they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * are halved if the mode bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 					    unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct ccu_common *cm = hw_to_ccu_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u32 val = readl(cm->base + cm->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (val & CCU_MMC_NEW_TIMING_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int ccu_mp_mmc_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				     struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct ccu_common *cm = hw_to_ccu_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32 val = readl(cm->base + cm->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* adjust the requested clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (val & CCU_MMC_NEW_TIMING_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		req->rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		req->min_rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		req->max_rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ret = ccu_mp_determine_rate(hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* re-adjust the requested clock rate back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (val & CCU_MMC_NEW_TIMING_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		req->rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		req->min_rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		req->max_rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			       unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct ccu_common *cm = hw_to_ccu_common(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	u32 val = readl(cm->base + cm->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (val & CCU_MMC_NEW_TIMING_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return ccu_mp_set_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const struct clk_ops ccu_mp_mmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.disable	= ccu_mp_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.enable		= ccu_mp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.is_enabled	= ccu_mp_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.get_parent	= ccu_mp_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.set_parent	= ccu_mp_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.determine_rate	= ccu_mp_mmc_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.recalc_rate	= ccu_mp_mmc_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.set_rate	= ccu_mp_mmc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };