Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _CCU_SUNIV_F1C100S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _CCU_SUNIV_F1C100S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_PLL_CPU		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PLL_AUDIO_BASE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_AUDIO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO_2X	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO_4X	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_8X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_VIDEO		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_VIDEO_2X	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PLL_VE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PLL_DDR0		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PLL_PERIPH		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* CPU clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_AHB			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_APB			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* All bus gates, DRAM gates and mod clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_NUMBER		(CLK_AVS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif /* _CCU_SUNIV_F1C100S_H_ */