Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2016 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN9I_A80_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN9I_A80_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun9i-a80-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/sun9i-a80-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PLL_C0CPUX		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_C1CPUX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* pll-audio and pll-periph0 are exported to the PRCM block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_VE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_DDR		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PLL_VIDEO0		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PLL_VIDEO1		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PLL_GPU		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_DE		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_ISP		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_PERIPH1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* The CPUX clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_ATB0		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_AXI0		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_ATB1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_AXI1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_GTBUS		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_AHB0		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_AHB1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_AHB2		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_APB0		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_APB1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_CCI400		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_ATS			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_TRACE		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* module clocks and bus gates exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_NUMBER		(CLK_BUS_UART5 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* _CCU_SUN9I_A80_H_ */