^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu-sun9i-a80.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCU_SUN9I_LOCK_REG 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * P should only be used for output frequencies lower than 228 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * For now we can just model it as a multiplier clock, and force P to /1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUN9I_A80_PLL_C0CPUX_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUN9I_A80_PLL_C1CPUX_REG 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct ccu_mult pll_c0cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .lock = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .reg = SUN9I_A80_PLL_C0CPUX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct ccu_mult pll_c1cpux_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .lock = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .reg = SUN9I_A80_PLL_C1CPUX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) &ccu_mult_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The Audio PLL has d1, d2 dividers in addition to the usual N, M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUN9I_A80_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct ccu_nm pll_audio_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .lock = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .reg = 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &ccu_nm_ops, CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct ccu_nkmp pll_periph0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .lock = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg = 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct ccu_nkmp pll_ve_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .lock = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .reg = 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct ccu_nkmp pll_ddr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .lock = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .reg = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct ccu_nm pll_video0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .lock = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .reg = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &ccu_nm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct ccu_nkmp pll_video1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .lock = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .reg = 0x01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct ccu_nkmp pll_gpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .lock = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .reg = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct ccu_nkmp pll_de_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .lock = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .reg = 0x024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .hw.init = CLK_HW_INIT("pll-de", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct ccu_nkmp pll_isp_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .lock = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .hw.init = CLK_HW_INIT("pll-isp", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct ccu_nkmp pll_periph1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .lock = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .p = _SUNXI_CCU_DIV(18, 1), /* output divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .lock_reg = CCU_SUN9I_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .features = CCU_FEATURE_LOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x50, 0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x50, 8, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct clk_div_table axi_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .val = 4, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .val = 5, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .val = 6, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .val = 7, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static SUNXI_CCU_M(atb0_clk, "atb0", "c0cpux", 0x054, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static SUNXI_CCU_DIV_TABLE(axi0_clk, "axi0", "c0cpux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x054, 0, 3, axi_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static SUNXI_CCU_M(atb1_clk, "atb1", "c1cpux", 0x058, 8, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static SUNXI_CCU_DIV_TABLE(axi1_clk, "axi1", "c1cpux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x058, 0, 3, axi_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const char * const gtbus_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "pll-periph1", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static SUNXI_CCU_M_WITH_MUX(gtbus_clk, "gtbus", gtbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char * const ahb_parents[] = { "gtbus", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "pll-periph1", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct ccu_div ahb0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .reg = 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .hw.init = CLK_HW_INIT_PARENTS("ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ahb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .reg = 0x064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ahb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct ccu_div ahb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .reg = 0x068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .hw.init = CLK_HW_INIT_PARENTS("ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ahb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char * const apb_parents[] = { "osc24M", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct ccu_div apb0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .mux = _SUNXI_CCU_MUX(24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .reg = 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .hw.init = CLK_HW_INIT_PARENTS("apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) apb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct ccu_div apb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .mux = _SUNXI_CCU_MUX(24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .reg = 0x074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .hw.init = CLK_HW_INIT_PARENTS("apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) apb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct ccu_div cci400_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .reg = 0x078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .hw.init = CLK_HW_INIT_PARENTS("cci400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ahb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", apb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x080, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", apb_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x084, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct ccu_mux_fixed_prediv out_prediv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .index = 0, .div = 750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct ccu_mp out_a_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .fixed_predivs = &out_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .n_predivs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .reg = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .hw.init = CLK_HW_INIT_PARENTS("out-a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct ccu_mp out_b_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .fixed_predivs = &out_prediv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .n_predivs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .reg = 0x184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .hw.init = CLK_HW_INIT_PARENTS("out-b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x40c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x410, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x410, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 0x414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0x414, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 0x414, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x418, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x418, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x41c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0x41c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0x41c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x428,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const char * const ss_parents[] = { "osc24M", "pll-periph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const u8 ss_table[] = { 0, 1, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct ccu_mp ss_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .m = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .mux = _SUNXI_CCU_MUX_TABLE(24, 4, ss_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .reg = 0x42c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .hw.init = CLK_HW_INIT_PARENTS("ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ss_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 0x430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x438,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x43c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const u8 sdram_table[] = { 0, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(sdram_clk, "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) sdram_parents, sdram_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 8, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 12, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0, /* no gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const u8 mp_table[] = { 9, 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x498,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const char * const display_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const u8 display_table[] = { 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd0_clk, "lcd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) display_parents, display_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x49c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) CLK_SET_RATE_NO_REPARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd1_clk, "lcd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) display_parents, display_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x4a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) CLK_SET_RATE_NO_REPARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) display_parents, display_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 0x4a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const u8 mipi_dsi1_table[] = { 0, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mipi_dsi1_parents, mipi_dsi1_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0x4ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) display_parents, display_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0x4b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) CLK_SET_RATE_NO_REPARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0, 4, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mipi_dsi1_parents, mipi_dsi1_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 0x4c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mipi_dsi1_parents, mipi_dsi1_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 0x4c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const fd_parents[] = { "pll-periph0", "pll-isp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const u8 fd_table[] = { 1, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(fd_clk, "fd", fd_parents, fd_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x4cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 16, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const u8 gpu_axi_table[] = { 1, 10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) gpu_axi_parents, gpu_axi_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 0x4f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0, 4, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mod0_default_parents, 0x508,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const u8 gpadc_table[] = { 0, 4, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct ccu_mp gpadc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .m = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .mux = _SUNXI_CCU_MUX_TABLE(24, 4, gpadc_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .reg = 0x50c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .hw.init = CLK_HW_INIT_PARENTS("gpadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) gpadc_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const char * const cir_tx_parents[] = { "osc24M", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const u8 cir_tx_table[] = { 0, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static struct ccu_mp cir_tx_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .m = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .mux = _SUNXI_CCU_MUX_TABLE(24, 4, cir_tx_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .reg = 0x510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .hw.init = CLK_HW_INIT_PARENTS("cir-tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cir_tx_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* AHB0 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0x580, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 0x580, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 0x580, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 0x580, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 0x580, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 0x580, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 0x580, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 0x580, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 0x580, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 0x580, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0x580, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 0x580, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 0x580, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 0x580, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 0x580, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* AHB1 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 0x584, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 0x584, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 0x584, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 0x584, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 0x584, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 0x584, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 0x584, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* AHB2 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 0x588, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 0x588, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 0x588, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 0x588, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 0x588, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 0x588, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 0x588, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 0x588, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* APB0 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 0x590, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 0x590, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 0x590, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 0x590, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 0x590, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 0x590, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0x590, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 0x590, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 0x590, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* APB1 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 0x594, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 0x594, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 0x594, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 0x594, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 0x594, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 0x594, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 0x594, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 0x594, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 0x594, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 0x594, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 0x594, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static struct ccu_common *sun9i_a80_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) &pll_c0cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &pll_c1cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) &pll_audio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &pll_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) &c0cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) &c1cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &atb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) &axi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &atb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) &axi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) >bus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &ahb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) &apb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &cci400_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &ats_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &trace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) &out_a_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &out_b_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* module clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &nand0_0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &nand0_1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &nand1_0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &nand1_1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) &mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &mmc3_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &mmc3_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &sdram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &edp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &lcd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &mipi_dsi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &mipi_dsi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &hdmi_slow_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &mipi_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &csi_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &csi0_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &csi1_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &fd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &gpu_core_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) &gpu_memory_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &gpu_axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) &ac97_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &mipi_hsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &gpadc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &cir_tx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* AHB0 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &bus_fd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &bus_gpu_ctrl_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &bus_ss_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &bus_mmc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &bus_nand0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &bus_nand1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &bus_sdram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) &bus_mipi_hsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) &bus_sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &bus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &bus_spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &bus_spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* AHB1 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &bus_usb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) &bus_gmac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* AHB2 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &bus_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &bus_lcd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &bus_edp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) &bus_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) &bus_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) &bus_mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* APB0 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) &bus_ac97_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) &bus_lradc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &bus_gpadc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &bus_twd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &bus_cir_tx_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* APB1 bus gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) &bus_i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) &bus_i2c4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) &bus_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) &bus_uart5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static struct clk_hw_onecell_data sun9i_a80_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [CLK_C0CPUX] = &c0cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [CLK_C1CPUX] = &c1cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) [CLK_ATB0] = &atb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [CLK_AXI0] = &axi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [CLK_ATB1] = &atb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [CLK_AXI1] = &axi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [CLK_GTBUS] = >bus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [CLK_AHB0] = &ahb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [CLK_APB0] = &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [CLK_CCI400] = &cci400_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [CLK_ATS] = &ats_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [CLK_TRACE] = &trace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [CLK_OUT_A] = &out_a_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [CLK_OUT_B] = &out_b_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [CLK_NAND0_0] = &nand0_0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [CLK_NAND0_1] = &nand0_1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [CLK_NAND1_0] = &nand1_0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [CLK_NAND1_1] = &nand1_1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [CLK_MMC3] = &mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [CLK_SS] = &ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [CLK_SPI3] = &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [CLK_SDRAM] = &sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [CLK_EDP] = &edp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [CLK_MP] = &mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [CLK_LCD0] = &lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [CLK_LCD1] = &lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [CLK_CSI_ISP] = &csi_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [CLK_FD] = &fd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [CLK_GPU_AXI] = &gpu_axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [CLK_SATA] = &sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [CLK_AC97] = &ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [CLK_MIPI_HSI] = &mipi_hsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [CLK_GPADC] = &gpadc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [CLK_CIR_TX] = &cir_tx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [CLK_BUS_FD] = &bus_fd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [CLK_BUS_GPU_CTRL] = &bus_gpu_ctrl_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [CLK_BUS_SS] = &bus_ss_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [CLK_BUS_MMC] = &bus_mmc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [CLK_BUS_NAND0] = &bus_nand0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [CLK_BUS_NAND1] = &bus_nand1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [CLK_BUS_SDRAM] = &bus_sdram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [CLK_BUS_MIPI_HSI] = &bus_mipi_hsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [CLK_BUS_SATA] = &bus_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [CLK_BUS_TS] = &bus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [CLK_BUS_USB] = &bus_usb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [CLK_BUS_LCD0] = &bus_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [CLK_BUS_LCD1] = &bus_lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [CLK_BUS_EDP] = &bus_edp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [CLK_BUS_MP] = &bus_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [CLK_BUS_TWD] = &bus_twd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [CLK_BUS_CIR_TX] = &bus_cir_tx_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static struct ccu_reset_map sun9i_a80_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* AHB0 reset controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [RST_BUS_FD] = { 0x5a0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [RST_BUS_VE] = { 0x5a0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [RST_BUS_SS] = { 0x5a0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [RST_BUS_MMC] = { 0x5a0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [RST_BUS_NAND0] = { 0x5a0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [RST_BUS_NAND1] = { 0x5a0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [RST_BUS_SDRAM] = { 0x5a0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [RST_BUS_SATA] = { 0x5a0, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [RST_BUS_TS] = { 0x5a0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [RST_BUS_SPI0] = { 0x5a0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [RST_BUS_SPI1] = { 0x5a0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [RST_BUS_SPI2] = { 0x5a0, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [RST_BUS_SPI3] = { 0x5a0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* AHB1 reset controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [RST_BUS_OTG] = { 0x5a4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [RST_BUS_GMAC] = { 0x5a4, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [RST_BUS_DMA] = { 0x5a4, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* AHB2 reset controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [RST_BUS_LCD0] = { 0x5a8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [RST_BUS_LCD1] = { 0x5a8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [RST_BUS_EDP] = { 0x5a8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [RST_BUS_LVDS] = { 0x5a8, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [RST_BUS_CSI] = { 0x5a8, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [RST_BUS_HDMI0] = { 0x5a8, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [RST_BUS_HDMI1] = { 0x5a8, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [RST_BUS_DE] = { 0x5a8, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [RST_BUS_MP] = { 0x5a8, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [RST_BUS_GPU] = { 0x5a8, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* APB0 reset controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) [RST_BUS_SPDIF] = { 0x5b0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [RST_BUS_AC97] = { 0x5b0, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [RST_BUS_I2S0] = { 0x5b0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [RST_BUS_I2S1] = { 0x5b0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [RST_BUS_LRADC] = { 0x5b0, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [RST_BUS_GPADC] = { 0x5b0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* APB1 reset controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [RST_BUS_I2C0] = { 0x5b4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [RST_BUS_I2C1] = { 0x5b4, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [RST_BUS_I2C2] = { 0x5b4, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [RST_BUS_I2C3] = { 0x5b4, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [RST_BUS_I2C4] = { 0x5b4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [RST_BUS_UART0] = { 0x5b4, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [RST_BUS_UART1] = { 0x5b4, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [RST_BUS_UART2] = { 0x5b4, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [RST_BUS_UART3] = { 0x5b4, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [RST_BUS_UART4] = { 0x5b4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [RST_BUS_UART5] = { 0x5b4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .ccu_clks = sun9i_a80_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .num_ccu_clks = ARRAY_SIZE(sun9i_a80_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .hw_clks = &sun9i_a80_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .resets = sun9i_a80_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SUN9I_A80_PLL_P_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define SUN9I_A80_PLL_N_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define SUN9I_A80_PLL_N_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static void sun9i_a80_cpu_pll_fixup(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* bail out if P divider is not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * If P is used, output should be less than 288 MHz. When we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * set P to 1, we should also decrease the multiplier so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * output doesn't go out of range, but not too much such that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * the multiplier stays above 12, the minimal operation value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * To keep it simple, set the multiplier to 17, the reset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) SUN9I_A80_PLL_N_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) val |= 17 << SUN9I_A80_PLL_N_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* And clear P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) val &= ~BIT(SUN9I_A80_PLL_P_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static int sun9i_a80_ccu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* Enforce d1 = 0, d2 = 0 for Audio PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) val = readl(reg + SUN9I_A80_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) val &= ~(BIT(16) | BIT(18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* Enforce P = 1 for both CPU cluster PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C0CPUX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C1CPUX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const struct of_device_id sun9i_a80_ccu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) { .compatible = "allwinner,sun9i-a80-ccu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static struct platform_driver sun9i_a80_ccu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .probe = sun9i_a80_ccu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .name = "sun9i-a80-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .of_match_table = sun9i_a80_ccu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) builtin_platform_driver(sun9i_a80_ccu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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