Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2016 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN9I_A80_DE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN9I_A80_DE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun9i-a80-de.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/sun9i-a80-de.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Intermediary clock dividers are not exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_FE0_DIV	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_FE1_DIV	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_FE2_DIV	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_BE0_DIV	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_BE1_DIV	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_BE2_DIV	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_NUMBER	(CLK_BE2_DIV + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif /* _CCU_SUN9I_A80_DE_H_ */