^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu-sun9i-a80-de.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 0x00, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 0x00, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 0x00, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0x00, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 0x00, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 0x00, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0x00, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 0x00, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0x00, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x00, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static SUNXI_CCU_GATE(merge_clk, "merge", "de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0x00, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x04, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0x04, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0x04, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x04, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x04, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x04, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x04, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x04, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x04, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x04, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x08, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x08, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x08, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x08, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x08, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x08, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x08, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x08, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x08, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x08, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct ccu_common *sun9i_a80_de_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) &fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &fe2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) &iep_deu0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &iep_deu1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) &be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) &be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &be2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) &iep_drc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &iep_drc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) &merge_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &dram_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &dram_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) &dram_fe2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) &dram_deu0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &dram_deu1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) &dram_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) &dram_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) &dram_be2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) &dram_drc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) &dram_drc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) &bus_fe0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &bus_fe1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) &bus_fe2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &bus_deu0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &bus_deu1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &bus_be0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &bus_be1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &bus_be2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &bus_drc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &bus_drc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &fe0_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) &fe1_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &fe2_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &be0_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &be1_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &be2_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [CLK_FE0] = &fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [CLK_FE1] = &fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [CLK_FE2] = &fe2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [CLK_BE0] = &be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [CLK_BE1] = &be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [CLK_BE2] = &be2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [CLK_MERGE] = &merge_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [CLK_DRAM_FE2] = &dram_fe2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [CLK_DRAM_BE2] = &dram_be2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [CLK_BUS_FE0] = &bus_fe0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [CLK_BUS_FE1] = &bus_fe1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [CLK_BUS_FE2] = &bus_fe2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [CLK_BUS_DEU0] = &bus_deu0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [CLK_BUS_DEU1] = &bus_deu1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [CLK_BUS_BE0] = &bus_be0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [CLK_BUS_BE1] = &bus_be1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [CLK_BUS_BE2] = &bus_be2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [CLK_BUS_DRC0] = &bus_drc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [CLK_BUS_DRC1] = &bus_drc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [CLK_FE0_DIV] = &fe0_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [CLK_FE1_DIV] = &fe1_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [CLK_FE2_DIV] = &fe2_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [CLK_BE0_DIV] = &be0_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [CLK_BE1_DIV] = &be1_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [CLK_BE2_DIV] = &be2_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct ccu_reset_map sun9i_a80_de_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [RST_FE0] = { 0x0c, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [RST_FE1] = { 0x0c, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [RST_FE2] = { 0x0c, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [RST_DEU0] = { 0x0c, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [RST_DEU1] = { 0x0c, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [RST_BE0] = { 0x0c, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [RST_BE1] = { 0x0c, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [RST_BE2] = { 0x0c, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [RST_DRC0] = { 0x0c, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [RST_DRC1] = { 0x0c, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [RST_MERGE] = { 0x0c, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct sunxi_ccu_desc sun9i_a80_de_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ccu_clks = sun9i_a80_de_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .num_ccu_clks = ARRAY_SIZE(sun9i_a80_de_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .hw_clks = &sun9i_a80_de_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .resets = sun9i_a80_de_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .num_resets = ARRAY_SIZE(sun9i_a80_de_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int sun9i_a80_de_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bus_clk = devm_clk_get(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = PTR_ERR(bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "Couldn't get reset control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* The bus clock needs to be enabled for us to access the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = clk_prepare_enable(bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* The reset control needs to be asserted for the controls to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "Couldn't deassert reset control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = sunxi_ccu_probe(pdev->dev.of_node, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &sun9i_a80_de_clk_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto err_assert_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) err_assert_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk_disable_unprepare(bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct of_device_id sun9i_a80_de_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { .compatible = "allwinner,sun9i-a80-de-clks" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct platform_driver sun9i_a80_de_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .probe = sun9i_a80_de_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "sun9i-a80-de-clks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .of_match_table = sun9i_a80_de_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) builtin_platform_driver(sun9i_a80_de_clk_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags