Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Based on ccu-sun8i-h3.h, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _CCU_SUN8I_H3_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _CCU_SUN8I_H3_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/sun8i-v3s-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/reset/sun8i-v3s-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_CPU		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO_BASE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_2X	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_AUDIO_4X	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_PLL_AUDIO_8X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PLL_VIDEO		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PLL_VE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PLL_DDR0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_PERIPH0		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_PERIPH0_2X	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_ISP		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_PLL_PERIPH1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Reserve one number for not implemented and not used PLL_DDR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* The CPU clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_AXI			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_AHB1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_APB1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_APB2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_AHB2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* All the bus gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* The first bunch of module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_DRAM		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* All the DRAM gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Some more module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_MBUS		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* And the GPU module clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_PLL_DDR1		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif /* _CCU_SUN8I_H3_H_ */