^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on ccu-sun8i-h3.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ccu-sun8i-v3s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "osc24M", 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * We don't have any need for the variable divider for now, so we just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * hardcode it to match with the clock names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN8I_V3S_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "osc24M", 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "osc24M", 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "osc24M", 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "osc24M", 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "osc24M", 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "osc24M", 0x002c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "osc24M", 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "osc24M", 0x04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const char * const cpu_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "pll-cpu", "pll-cpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x050, 16, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char * const ahb1_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "axi", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct clk_div_table apb1_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x054, 8, 2, apb1_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const char * const apb2_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "pll-periph0", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .index = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct ccu_mux ahb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .fixed_predivs = ahb2_fixed_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .reg = 0x05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .hw.init = CLK_HW_INIT_PARENTS("ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ahb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x070, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x070, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x088, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x088, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x08c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0x08c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x090, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x090, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x100, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x100, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const char * const de_parents[] = { "pll-video", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x104, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const char * const tcon_parents[] = { "pll-video" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x118, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x130, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x130, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0x134, 16, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x134, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x13c, 16, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "pll-isp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x16c, 0, 3, 24, 2, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct ccu_common *sun8i_v3s_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &pll_cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) &pll_video_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) &pll_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) &pll_ddr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &bus_tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &bus_ephy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &dram_ohci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &dram_ehci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &tcon_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &csi0_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &csi1_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &csi1_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &ac_dig_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &mipi_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct ccu_common *sun8i_v3_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) &pll_cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &pll_video_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &pll_isp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &pll_ddr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &bus_tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &bus_ephy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) &dram_ohci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &dram_ehci_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &tcon_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) &csi0_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &csi1_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &csi1_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &ac_dig_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &mipi_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* We hardcode the divider to 4 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 4, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [CLK_TCON0] = &tcon_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) [CLK_AC_DIG] = &ac_dig_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .num = CLK_PLL_DDR1 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [CLK_TCON0] = &tcon_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [CLK_AC_DIG] = &ac_dig_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .num = CLK_I2S0 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [RST_BUS_CE] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [RST_BUS_OTG] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [RST_BUS_DBG] = { 0x2c4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [RST_BUS_CE] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [RST_BUS_OTG] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [RST_BUS_DBG] = { 0x2c4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .ccu_clks = sun8i_v3s_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .hw_clks = &sun8i_v3s_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .resets = sun8i_v3s_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .ccu_clks = sun8i_v3_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .hw_clks = &sun8i_v3_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .resets = sun8i_v3_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) const struct sunxi_ccu_desc *ccu_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Force the PLL-Audio-1x divider to 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) val &= ~GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) sunxi_ccu_probe(node, reg, ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static void __init sun8i_v3s_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static void __init sun8i_v3_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) sun8i_v3s_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) sun8i_v3_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags