Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _CCU_SUN8I_R40_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _CCU_SUN8I_R40_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <dt-bindings/clock/sun8i-r40-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/reset/sun8i-r40-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_OSC_12M		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_PLL_CPU		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PLL_AUDIO_BASE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_AUDIO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO_2X	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO_4X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_8X	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* PLL_VIDEO0 is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PLL_VIDEO0_2X	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PLL_VE		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_DDR0		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_PLL_PERIPH0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_PLL_PERIPH0_SATA	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_PLL_PERIPH0_2X	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_PLL_PERIPH1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PLL_PERIPH1_2X	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PLL_VIDEO1 is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_PLL_VIDEO1_2X	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_PLL_SATA		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_PLL_SATA_OUT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_PLL_GPU		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_PLL_MIPI		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_PLL_DE		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_PLL_DDR1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* The CPU clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_AXI			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_AHB1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_APB1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_APB2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* All the bus gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* The first bunch of module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_DRAM		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* All the DRAM gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Some more module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_NUMBER		(CLK_OUTB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif /* _CCU_SUN8I_R40_H_ */