^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu-sun8i-r40.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* TODO: The result of N*K is required to be in [10, 88] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct ccu_nkmp pll_cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .reg = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .hw.init = CLK_HW_INIT("pll-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) &ccu_nkmp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUN8I_R40_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "osc24M", 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x284, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "osc24M", 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 192000000, /* Minimum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 1008000000, /* Maximum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* TODO: The result of N/M is required to be in [8, 25] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "osc24M", 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* TODO: The result of N*K is required to be in [10, 77] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "osc24M", 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* TODO: The result of N*K is required to be in [21, 58] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct ccu_nk pll_periph0_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct ccu_div pll_periph0_sata_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .enable = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .div = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 6/2 = 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .fixed_post_div = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .reg = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .hw.init = CLK_HW_INIT("pll-periph0-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &ccu_div_ops, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* TODO: The result of N*K is required to be in [21, 58] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct ccu_nk pll_periph1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .fixed_post_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .reg = 0x02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) &ccu_nk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "osc24M", 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 192000000, /* Minimum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 1008000000, /* Maximum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct ccu_nkm pll_sata_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .n = _SUNXI_CCU_MULT(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .k = _SUNXI_CCU_MULT(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .m = _SUNXI_CCU_DIV(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .fixed_post_div = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg = 0x034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .features = CCU_FEATURE_FIXED_POSTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &ccu_nkm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CLK_SET_RATE_UNGATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const char * const pll_sata_out_parents[] = { "pll-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "pll-periph0-sata" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pll_sata_out_parents, 0x034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 30, 1, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BIT(14), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* TODO: The result of N/M is required to be in [8, 25] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "osc24M", 0x038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * integer / fractional clock with switchable multipliers and dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * This is not supported here. We hardcode the PLL to MIPI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * which cannot be implemented now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SUN8I_R40_PLL_MIPI_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const char * const pll_mipi_parents[] = { "pll-video0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct ccu_nkm pll_mipi_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .enable = BIT(31) | BIT(23) | BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .n = _SUNXI_CCU_MULT(8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .m = _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .mux = _SUNXI_CCU_MUX(21, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .reg = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pll_mipi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &ccu_nkm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CLK_SET_RATE_UNGATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* TODO: The result of N/M is required to be in [8, 25] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "osc24M", 0x048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* TODO: The N factor is required to be in [16, 75] range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "osc24M", 0x04c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char * const cpu_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "pll-cpu", "pll-cpu" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const ahb1_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "axi", "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct clk_div_table apb1_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x054, 8, 2, apb1_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char * const apb2_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x060, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x060, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x060, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x060, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0x060, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x060, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x060, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0x060, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x060, BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x060, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x064, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x064, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x064, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x064, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x064, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x064, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x064, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x064, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x064, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x064, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x064, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x064, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x064, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x064, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x064, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x064, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x064, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x064, BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 0x068, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x068, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x068, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0x068, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x068, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x068, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x068, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x06c, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * In datasheet here's "Reserved", however the gate exists in BSP soucre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x06c, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x06c, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x06c, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x06c, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x06c, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0x06c, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x06c, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 0x06c, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0x070, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const char * const ths_parents[] = { "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct ccu_div ths_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .mux = _SUNXI_CCU_MUX(24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .reg = 0x074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .hw.init = CLK_HW_INIT_PARENTS("ths",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ths_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 24, 4, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "pll-periph1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const char * const keypad_parents[] = { "osc24M", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const u8 keypad_table[] = { 0, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct ccu_mp keypad_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .m = _SUNXI_CCU_DIV(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .p = _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .reg = 0x0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .hw.init = CLK_HW_INIT_PARENTS("keypad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) keypad_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * There are 3 OHCI 12M clock source selection bits in this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * We will force them to 0 (12M divided from 48M).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SUN8I_R40_USB_CLK_REG 0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0x0cc, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 0x0cc, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0x0cc, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char * const ir_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "pll-periph1", "osc32k" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 0x100, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x100, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0x100, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 0x100, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0x100, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0x104, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 0x108, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "pll-video0-2x", "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "pll-mipi" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0x118, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 0x11c, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const char * const deinterlace_parents[] = { "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) deinterlace_parents, 0x124, 0, 4, 24, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 0x130, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0x134, 16, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 0x134, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 0x150, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0x154, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * In the SoC's user manual, the P factor is mentioned, but not used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * the frequency formula.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Here the factor is included, according to the BSP kernel source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * which contains the P factor of this clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "pll-ddr0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 0x168, 0, 4, 8, 2, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 0x180, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 0x184, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "pll-video0-2x", "pll-video1-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 0x188, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 0x18c, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 0x190, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 0x194, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct ccu_mux_fixed_prediv out_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { .index = 0, .div = 750, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static struct ccu_mp outa_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .fixed_predivs = out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .n_predivs = ARRAY_SIZE(out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .reg = 0x1f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static struct ccu_mp outb_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .m = _SUNXI_CCU_DIV(8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .p = _SUNXI_CCU_DIV(20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .fixed_predivs = out_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .n_predivs = ARRAY_SIZE(out_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .reg = 0x1f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static struct ccu_common *sun8i_r40_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) &pll_cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) &pll_video0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) &pll_ddr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) &pll_periph0_sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) &pll_video1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &pll_sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) &pll_sata_out_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &pll_mipi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &pll_ddr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) &bus_mipi_dsi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) &bus_mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &bus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) &bus_spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) &bus_spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) &bus_sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) &bus_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) &bus_ehci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &bus_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) &bus_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) &bus_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) &bus_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &bus_csi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &bus_csi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) &bus_hdmi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) &bus_hdmi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &bus_tve0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &bus_tve1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &bus_tve_top_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &bus_gmac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &bus_tvd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &bus_tvd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &bus_tvd2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) &bus_tvd3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &bus_tvd_top_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) &bus_tcon_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) &bus_tcon_lcd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) &bus_tcon_tv0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &bus_tcon_tv1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) &bus_tcon_top_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) &bus_ac97_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) &bus_ir0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) &bus_ir1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) &bus_ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &bus_keypad_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &bus_i2c3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &bus_can_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) &bus_scr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &bus_ps20_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) &bus_ps21_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) &bus_i2c4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &bus_uart4_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) &bus_uart5_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) &bus_uart6_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &bus_uart7_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &mmc3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) &spi2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &spi3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) &ac97_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) &keypad_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) &sata_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) &usb_phy2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &usb_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) &ir0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) &ir1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &dram_csi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &dram_csi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) &dram_tvd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) &dram_mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) &dram_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) &mp_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) &tcon_lcd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &tcon_lcd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &tcon_tv0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &tcon_tv1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) &deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) &csi1_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) &csi0_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &hdmi_slow_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) &dsi_dphy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &tve0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) &tve1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &tvd0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) &tvd1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &tvd2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) &tvd3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &outa_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) &outb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Fixed Factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* We hardcode the divider to 1 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [CLK_OSC_12M] = &osc12M_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [CLK_PLL_SATA] = &pll_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [CLK_CPU] = &cpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [CLK_BUS_TS] = &bus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [CLK_BUS_SATA] = &bus_sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [CLK_BUS_MP] = &bus_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [CLK_BUS_IR0] = &bus_ir0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [CLK_BUS_IR1] = &bus_ir1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [CLK_BUS_THS] = &bus_ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) [CLK_BUS_CAN] = &bus_can_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [CLK_BUS_PS20] = &bus_ps20_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [CLK_BUS_PS21] = &bus_ps21_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [CLK_THS] = &ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [CLK_MMC3] = &mmc3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [CLK_SPI2] = &spi2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [CLK_SPI3] = &spi3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [CLK_AC97] = &ac97_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [CLK_KEYPAD] = &keypad_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [CLK_SATA] = &sata_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [CLK_IR0] = &ir0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) [CLK_IR1] = &ir1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [CLK_MP] = &mp_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [CLK_CODEC] = &codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [CLK_TVE0] = &tve0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) [CLK_TVE1] = &tve1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [CLK_TVD0] = &tvd0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [CLK_TVD1] = &tvd1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [CLK_TVD2] = &tvd2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [CLK_TVD3] = &tvd3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [CLK_OUTA] = &outa_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [CLK_OUTB] = &outb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .num = CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [RST_USB_PHY2] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [RST_DRAM] = { 0x0f4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [RST_BUS_CE] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [RST_BUS_NAND] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) [RST_BUS_TS] = { 0x2c0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [RST_BUS_SATA] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [RST_BUS_OTG] = { 0x2c0, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) [RST_BUS_MP] = { 0x2c4, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) [RST_BUS_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) [RST_BUS_DBG] = { 0x2c4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) [RST_BUS_AC97] = { 0x2d0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) [RST_BUS_IR0] = { 0x2d0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) [RST_BUS_IR1] = { 0x2d0, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) [RST_BUS_THS] = { 0x2d0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) [RST_BUS_CAN] = { 0x2d8, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) [RST_BUS_SCR] = { 0x2d8, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) [RST_BUS_PS20] = { 0x2d8, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) [RST_BUS_PS21] = { 0x2d8, BIT(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) [RST_BUS_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) [RST_BUS_UART4] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) [RST_BUS_UART5] = { 0x2d8, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) [RST_BUS_UART6] = { 0x2d8, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) [RST_BUS_UART7] = { 0x2d8, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .ccu_clks = sun8i_r40_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .hw_clks = &sun8i_r40_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .resets = sun8i_r40_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .common = &pll_cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* copy from pll_cpu_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static struct ccu_mux_nb sun8i_r40_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .common = &cpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .cm = &cpu_clk.mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .delay_us = 1, /* > 8 clock cycles at 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .bypass_index = 1, /* index of 24 MHz oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * GMAC configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * Only this register is allowed to be written, in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * prevent overriding critical clock configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define SUN8I_R40_GMAC_CFG_REG 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (reg == SUN8I_R40_GMAC_CFG_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static struct regmap_config sun8i_r40_ccu_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* other devices have no business accessing other registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define SUN8I_R40_SYS_32K_CLK_REG 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static int sun8i_r40_ccu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) val &= ~GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Force PLL-MIPI to MIPI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) val &= ~BIT(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* Force OHCI 12M parent to 12M divided from 48M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) val = readl(reg + SUN8I_R40_USB_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) val &= ~GENMASK(25, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) writel(val, reg + SUN8I_R40_USB_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * Force SYS 32k (otherwise known as LOSC throughout the CCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * clock parent to LOSC output from RTC module instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * CCU's internal RC oscillator divided output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) reg + SUN8I_R40_SYS_32K_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) regmap = devm_regmap_init_mmio(&pdev->dev, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) &sun8i_r40_ccu_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* Gate then ungate PLL CPU after any rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Reparent CPU during PLL CPU rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) &sun8i_r40_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static const struct of_device_id sun8i_r40_ccu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) { .compatible = "allwinner,sun8i-r40-ccu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static struct platform_driver sun8i_r40_ccu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .probe = sun8i_r40_ccu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .name = "sun8i-r40-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .of_match_table = sun8i_r40_ccu_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) builtin_platform_driver(sun8i_r40_ccu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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