Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "ccu-sun8i-r.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static const struct clk_parent_data ar100_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	{ .fw_name = "losc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	{ .fw_name = "hosc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{ .fw_name = "pll-periph" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{ .fw_name = "iosc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static const struct ccu_mux_var_prediv ar100_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{ .index = 2, .shift = 8, .width = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static struct ccu_div ar100_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.mux		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.shift	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.width	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.var_predivs	= ar100_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.n_var_predivs	= ARRAY_SIZE(ar100_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.common		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.reg		= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("ar100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 							   ar100_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 							   &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 							   0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * Define the parent as an array that can be reused to save space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * instead of having compound literals for each gate. Also have it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * non-const so we can change it on the A83T.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static SUNXI_CCU_GATE_HWS(apb0_pio_clk,		"apb0-pio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			  apb0_gate_parent, 0x28, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static SUNXI_CCU_GATE_HWS(apb0_ir_clk,		"apb0-ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			  apb0_gate_parent, 0x28, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static SUNXI_CCU_GATE_HWS(apb0_timer_clk,	"apb0-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			  apb0_gate_parent, 0x28, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static SUNXI_CCU_GATE_HWS(apb0_rsb_clk,		"apb0-rsb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			  apb0_gate_parent, 0x28, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static SUNXI_CCU_GATE_HWS(apb0_uart_clk,	"apb0-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			  apb0_gate_parent, 0x28, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static SUNXI_CCU_GATE_HWS(apb0_i2c_clk,		"apb0-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			  apb0_gate_parent, 0x28, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static SUNXI_CCU_GATE_HWS(apb0_twd_clk,		"apb0-twd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			  apb0_gate_parent, 0x28, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				  r_mod0_default_parents, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				  0, 4,		/* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				  16, 2,	/* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				  24, 2,	/* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				  BIT(31),	/* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				  0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static const struct clk_parent_data a83t_r_mod0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ .fw_name = "iosc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ .fw_name = "hosc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ .index = 0, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct ccu_mp a83t_ir_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.enable	= BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.m	= _SUNXI_CCU_DIV(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.p	= _SUNXI_CCU_DIV(16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.mux	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.shift	= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.width	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.fixed_predivs	= a83t_ir_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.n_predivs	= ARRAY_SIZE(a83t_ir_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.common		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.reg		= 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.hw.init	= CLK_HW_INIT_PARENTS_DATA("ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 							   a83t_r_mod0_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 							   &ccu_mp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 							   0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	&ar100_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	&apb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	&apb0_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	&apb0_ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	&apb0_timer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	&apb0_rsb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	&apb0_uart_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	&apb0_i2c_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	&apb0_twd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	&a83t_ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	&ar100_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	&apb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	&apb0_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	&apb0_ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	&apb0_timer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	&apb0_uart_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	&apb0_i2c_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	&apb0_twd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	&ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	&ar100_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	&apb0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	&apb0_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	&apb0_ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	&apb0_timer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	&apb0_rsb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	&apb0_uart_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	&apb0_i2c_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	&apb0_twd_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	&ir_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		[CLK_AR100]		= &ar100_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		[CLK_AHB0]		= &ahb0_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		[CLK_APB0]		= &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		[CLK_APB0_IR]		= &apb0_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		[CLK_APB0_TIMER]	= &apb0_timer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		[CLK_APB0_RSB]		= &apb0_rsb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		[CLK_APB0_UART]		= &apb0_uart_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		[CLK_APB0_I2C]		= &apb0_i2c_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		[CLK_APB0_TWD]		= &apb0_twd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		[CLK_IR]		= &a83t_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.num	= CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		[CLK_AR100]		= &ar100_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		[CLK_AHB0]		= &ahb0_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		[CLK_APB0]		= &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		[CLK_APB0_IR]		= &apb0_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		[CLK_APB0_TIMER]	= &apb0_timer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		[CLK_APB0_UART]		= &apb0_uart_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		[CLK_APB0_I2C]		= &apb0_i2c_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		[CLK_APB0_TWD]		= &apb0_twd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		[CLK_IR]		= &ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.num	= CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		[CLK_AR100]		= &ar100_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		[CLK_AHB0]		= &ahb0_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		[CLK_APB0]		= &apb0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		[CLK_APB0_IR]		= &apb0_ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		[CLK_APB0_TIMER]	= &apb0_timer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		[CLK_APB0_RSB]		= &apb0_rsb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		[CLK_APB0_UART]		= &apb0_uart_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		[CLK_APB0_I2C]		= &apb0_i2c_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		[CLK_APB0_TWD]		= &apb0_twd_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		[CLK_IR]		= &ir_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.num	= CLK_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	[RST_APB0_IR]		=  { 0xb0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	[RST_APB0_TIMER]	=  { 0xb0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	[RST_APB0_RSB]		=  { 0xb0, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	[RST_APB0_UART]		=  { 0xb0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	[RST_APB0_I2C]		=  { 0xb0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	[RST_APB0_IR]		=  { 0xb0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	[RST_APB0_TIMER]	=  { 0xb0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	[RST_APB0_UART]		=  { 0xb0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	[RST_APB0_I2C]		=  { 0xb0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	[RST_APB0_IR]		=  { 0xb0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	[RST_APB0_TIMER]	=  { 0xb0, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	[RST_APB0_RSB]		=  { 0xb0, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	[RST_APB0_UART]		=  { 0xb0, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	[RST_APB0_I2C]		=  { 0xb0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.ccu_clks	= sun8i_a83t_r_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_r_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.hw_clks	= &sun8i_a83t_r_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.resets		= sun8i_a83t_r_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.num_resets	= ARRAY_SIZE(sun8i_a83t_r_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.ccu_clks	= sun8i_h3_r_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_r_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.hw_clks	= &sun8i_h3_r_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.resets		= sun8i_h3_r_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.num_resets	= ARRAY_SIZE(sun8i_h3_r_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.ccu_clks	= sun50i_a64_r_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_r_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.hw_clks	= &sun50i_a64_r_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.resets		= sun50i_a64_r_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.num_resets	= ARRAY_SIZE(sun50i_a64_r_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void __init sunxi_r_ccu_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				    const struct sunxi_ccu_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	sunxi_ccu_probe(node, reg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	       sun8i_a83t_r_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	       sun8i_h3_r_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	       sun50i_a64_r_ccu_setup);