Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _CCU_SUN8I_H3_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _CCU_SUN8I_H3_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/sun8i-h3-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/reset/sun8i-h3-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PLL_CPUX		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_AUDIO_BASE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_PLL_AUDIO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PLL_AUDIO_2X	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PLL_AUDIO_4X	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_PLL_AUDIO_8X	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PLL_VIDEO is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PLL_VE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_PLL_DDR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PLL_PERIPH0 exported for PRCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_PLL_PERIPH0_2X	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PLL_GPU		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_PLL_PERIPH1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_PLL_DE		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* The CPUX clock is exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_AXI			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_AHB1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_APB1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_APB2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_AHB2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* All the bus gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* The first bunch of module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_DRAM		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* All the DRAM gates are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Some more module clocks are exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_NUMBER_H3		(CLK_GPU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_NUMBER_H5		(CLK_BUS_SCR1 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif /* _CCU_SUN8I_H3_H_ */