^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Maxime Ripard. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "ccu_mp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "ccu_mult.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ccu_nk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ccu_nkm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "ccu_nkmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ccu_nm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ccu_phase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "ccu_sdm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccu-sun8i-h3.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "osc24M", 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * the base (2x, 4x and 8x), and one variable divider (the one true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * pll audio).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * With sigma-delta modulation for fractional-N on the audio PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * we have to use specific dividers. This means the variable divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * can no longer be used, as the audio codec requests the exact clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * rates we support through this mechanism. So we now hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * variable divider to 1. This means the clock rates will no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * match the clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN8I_H3_PLL_AUDIO_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct ccu_sdm_setting pll_audio_sdm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "osc24M", 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pll_audio_sdm_table, BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x284, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "osc24M", 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 192000000, /* Minimum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 912000000, /* Maximum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "osc24M", 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "osc24M", 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0, 2, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "osc24M", 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "osc24M", 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "osc24M", 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 8, 5, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 4, 2, /* K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 2, /* post-div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "osc24M", 0x0048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 8, 7, /* N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) BIT(24), /* frac enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) BIT(25), /* frac select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 270000000, /* frac rate 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 297000000, /* frac rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BIT(28), /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLK_SET_RATE_UNGATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const char * const cpux_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "pll-cpux" , "pll-cpux" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const ahb1_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "axi" , "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct ccu_mux_var_prediv ahb1_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .index = 3, .shift = 6, .width = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct ccu_div ahb1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .var_predivs = ahb1_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .reg = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .features = CCU_FEATURE_VARIABLE_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .hw.init = CLK_HW_INIT_PARENTS("ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ahb1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) &ccu_div_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct clk_div_table apb1_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .val = 0, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .val = 3, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x054, 8, 2, apb1_div_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const char * const apb2_parents[] = { "osc32k", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "pll-periph0" , "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0, 5, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .index = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct ccu_mux ahb2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .fixed_predivs = ahb2_fixed_predivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .reg = 0x05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .features = CCU_FEATURE_FIXED_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .hw.init = CLK_HW_INIT_PARENTS("ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ahb2_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &ccu_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x060, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0x060, BIT(6), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x060, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0x060, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x060, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x060, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x060, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x060, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x060, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x060, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x060, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0x060, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x060, BIT(23), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x060, BIT(24), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x060, BIT(25), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x060, BIT(26), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x060, BIT(27), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x060, BIT(28), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x060, BIT(29), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x060, BIT(30), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x060, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x064, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x064, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x064, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x064, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x064, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x064, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x064, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x064, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x064, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x064, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x064, BIT(22), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x068, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x068, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x068, BIT(5), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x068, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x068, BIT(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x068, BIT(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x068, BIT(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x06c, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x06c, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x06c, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x06c, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x06c, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x06c, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x06c, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x06c, BIT(20), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x06c, BIT(21), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x070, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x070, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct clk_div_table ths_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .val = 2, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .val = 3, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x074, 0, 2, ths_div_table, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x088, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x088, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x08c, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x08c, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x090, 20, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x090, 8, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0, 4, /* M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 16, 2, /* P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 24, 2, /* mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) BIT(31), /* gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "pll-audio-2x", "pll-audio" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x0cc, BIT(8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x0cc, BIT(9), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x0cc, BIT(10), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x0cc, BIT(11), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x0cc, BIT(16), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x0cc, BIT(17), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x0cc, BIT(18), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x0cc, BIT(19), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0x100, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0x100, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0x100, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0x100, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0x104, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const char * const tcon_parents[] = { "pll-video" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x118, 0, 4, 24, 3, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x120, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x124, 0, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x130, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x134, 16, 4, 24, 3, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0x134, 0, 5, 8, 3, BIT(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0x140, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0x144, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const char * const hdmi_parents[] = { "pll-video" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x150, 0, 4, 24, 2, BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0x154, BIT(31), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct ccu_common *sun8i_h3_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &pll_video_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &bus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &bus_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &bus_ehci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &bus_ehci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &bus_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &bus_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &bus_ohci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) &bus_tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &bus_tcon1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &bus_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &bus_tve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &bus_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &bus_ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &bus_scr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) &bus_ephy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) &ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) &mmc0_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &mmc0_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) &mmc1_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) &mmc1_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &mmc2_sample_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) &mmc2_output_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &usb_phy2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) &usb_phy3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) &usb_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) &usb_ohci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) &dram_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &tcon_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) &tve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) &deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &csi_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &ac_dig_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &hdmi_ddc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static struct ccu_common *sun50i_h5_ccu_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &pll_audio_base_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &pll_video_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) &pll_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &pll_ddr_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &pll_periph0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) &pll_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &pll_periph1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) &pll_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &axi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) &ahb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &apb1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &apb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &ahb2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &bus_ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) &bus_dma_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &bus_mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) &bus_mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) &bus_mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) &bus_nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) &bus_dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) &bus_emac_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &bus_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &bus_hstimer_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &bus_spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) &bus_spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) &bus_otg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) &bus_ehci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &bus_ehci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) &bus_ehci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) &bus_ehci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &bus_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) &bus_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) &bus_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) &bus_ohci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) &bus_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) &bus_tcon0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &bus_tcon1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) &bus_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) &bus_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) &bus_tve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) &bus_hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) &bus_de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) &bus_gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) &bus_msgbox_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &bus_spinlock_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) &bus_codec_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) &bus_spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &bus_pio_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &bus_ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &bus_i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) &bus_i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) &bus_i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) &bus_i2c0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &bus_i2c1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &bus_i2c2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) &bus_uart0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) &bus_uart1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) &bus_uart2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) &bus_uart3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) &bus_scr0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &bus_scr1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &bus_ephy_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) &bus_dbg_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) &ths_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) &nand_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) &mmc0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) &mmc1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &mmc2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) &ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) &ce_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) &spi0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &spi1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &i2s0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) &i2s1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &i2s2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &spdif_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &usb_phy0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) &usb_phy1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &usb_phy2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &usb_phy3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &usb_ohci0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &usb_ohci1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) &usb_ohci2_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) &usb_ohci3_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) &dram_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) &dram_ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) &dram_csi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &dram_deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) &dram_ts_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) &de_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) &tcon_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &tve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) &deinterlace_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) &csi_misc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) &csi_sclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) &csi_mclk_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &ve_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) &ac_dig_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) &avs_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) &hdmi_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) &hdmi_ddc_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &mbus_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &gpu_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct clk_hw *clk_parent_pll_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &pll_audio_base_clk.common.hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* We hardcode the divider to 1 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 2, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 1, 1, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk_parent_pll_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 1, 2, CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 1, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [CLK_CPUX] = &cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [CLK_BUS_TS] = &bus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [CLK_BUS_THS] = &bus_ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) [CLK_THS] = &ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [CLK_TCON0] = &tcon_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [CLK_TVE] = &tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) [CLK_AC_DIG] = &ac_dig_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .num = CLK_NUMBER_H3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) [CLK_PLL_VE] = &pll_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [CLK_PLL_DE] = &pll_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [CLK_CPUX] = &cpux_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [CLK_AXI] = &axi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) [CLK_AHB1] = &ahb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) [CLK_APB1] = &apb1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [CLK_APB2] = &apb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [CLK_AHB2] = &ahb2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) [CLK_BUS_CE] = &bus_ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [CLK_BUS_TS] = &bus_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [CLK_BUS_VE] = &bus_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) [CLK_BUS_DE] = &bus_de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) [CLK_BUS_THS] = &bus_ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) [CLK_THS] = &ths_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [CLK_NAND] = &nand_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [CLK_MMC0] = &mmc0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [CLK_MMC1] = &mmc1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) [CLK_MMC2] = &mmc2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) [CLK_TS] = &ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) [CLK_CE] = &ce_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) [CLK_SPI0] = &spi0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) [CLK_SPI1] = &spi1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [CLK_I2S0] = &i2s0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) [CLK_I2S1] = &i2s1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) [CLK_I2S2] = &i2s2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [CLK_SPDIF] = &spdif_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [CLK_DRAM] = &dram_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [CLK_DE] = &de_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [CLK_TCON0] = &tcon_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [CLK_TVE] = &tve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [CLK_VE] = &ve_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [CLK_AC_DIG] = &ac_dig_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [CLK_AVS] = &avs_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [CLK_HDMI] = &hdmi_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [CLK_MBUS] = &mbus_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [CLK_GPU] = &gpu_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .num = CLK_NUMBER_H5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [RST_USB_PHY2] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [RST_USB_PHY3] = { 0x0cc, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [RST_BUS_CE] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [RST_BUS_NAND] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [RST_BUS_TS] = { 0x2c0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [RST_BUS_OTG] = { 0x2c0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [RST_BUS_TVE] = { 0x2c4, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [RST_BUS_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [RST_BUS_DBG] = { 0x2c4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [RST_BUS_THS] = { 0x2d0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [RST_BUS_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [RST_USB_PHY0] = { 0x0cc, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [RST_USB_PHY1] = { 0x0cc, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [RST_USB_PHY2] = { 0x0cc, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [RST_USB_PHY3] = { 0x0cc, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [RST_MBUS] = { 0x0fc, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [RST_BUS_CE] = { 0x2c0, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [RST_BUS_DMA] = { 0x2c0, BIT(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [RST_BUS_NAND] = { 0x2c0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [RST_BUS_TS] = { 0x2c0, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [RST_BUS_OTG] = { 0x2c0, BIT(23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [RST_BUS_VE] = { 0x2c4, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [RST_BUS_CSI] = { 0x2c4, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [RST_BUS_TVE] = { 0x2c4, BIT(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [RST_BUS_DE] = { 0x2c4, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [RST_BUS_GPU] = { 0x2c4, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [RST_BUS_DBG] = { 0x2c4, BIT(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [RST_BUS_THS] = { 0x2d0, BIT(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [RST_BUS_UART0] = { 0x2d8, BIT(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [RST_BUS_UART1] = { 0x2d8, BIT(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [RST_BUS_UART2] = { 0x2d8, BIT(18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [RST_BUS_UART3] = { 0x2d8, BIT(19) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [RST_BUS_SCR1] = { 0x2d8, BIT(20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .ccu_clks = sun8i_h3_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .hw_clks = &sun8i_h3_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .resets = sun8i_h3_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .ccu_clks = sun50i_h5_ccu_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .num_ccu_clks = ARRAY_SIZE(sun50i_h5_ccu_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .hw_clks = &sun50i_h5_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .resets = sun50i_h5_ccu_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .common = &pll_cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* copy from pll_cpux_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .enable = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .lock = BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static struct ccu_mux_nb sun8i_h3_cpu_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .common = &cpux_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .cm = &cpux_clk.mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .delay_us = 1, /* > 8 clock cycles at 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .bypass_index = 1, /* index of 24 MHz oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) const struct sunxi_ccu_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) reg = of_io_request_and_map(node, 0, of_node_full_name(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) pr_err("%pOF: Could not map the clock registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Force the PLL-Audio-1x divider to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) val &= ~GENMASK(19, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) sunxi_ccu_probe(node, reg, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Gate then ungate PLL CPU after any rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Reparent CPU during PLL CPU rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) &sun8i_h3_cpu_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static void __init sun8i_h3_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) sun8i_h3_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static void __init sun50i_h5_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) sun50i_h5_ccu_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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