Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "ccu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "ccu_div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "ccu_gate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "ccu_reset.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "ccu-sun8i-de2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static SUNXI_CCU_GATE(bus_mixer0_clk,	"bus-mixer0",	"bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		      0x04, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static SUNXI_CCU_GATE(bus_mixer1_clk,	"bus-mixer1",	"bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		      0x04, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static SUNXI_CCU_GATE(bus_wb_clk,	"bus-wb",	"bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		      0x04, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static SUNXI_CCU_GATE(bus_rot_clk,	"bus-rot",	"bus-de",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		      0x04, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static SUNXI_CCU_GATE(mixer0_clk,	"mixer0",	"mixer0-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		      0x00, BIT(0), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static SUNXI_CCU_GATE(mixer1_clk,	"mixer1",	"mixer1-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		      0x00, BIT(1), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static SUNXI_CCU_GATE(wb_clk,		"wb",		"wb-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		      0x00, BIT(2), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static SUNXI_CCU_GATE(rot_clk,		"rot",		"rot-div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		      0x00, BIT(3), CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static SUNXI_CCU_M(rot_div_clk, "rot-div", "de", 0x0c, 0x0c, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		   CLK_SET_RATE_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct ccu_common *sun8i_a83t_de2_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	&mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	&mixer1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	&wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	&bus_mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	&bus_mixer1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	&bus_wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	&mixer0_div_a83_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	&mixer1_div_a83_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	&wb_div_a83_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	&bus_rot_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	&rot_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	&rot_div_a83_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static struct ccu_common *sun8i_h3_de2_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	&mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	&mixer1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	&wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	&bus_mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	&bus_mixer1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	&bus_wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	&mixer0_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	&mixer1_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	&wb_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static struct ccu_common *sun8i_v3s_de2_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	&mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	&wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	&bus_mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	&bus_wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	&mixer0_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	&wb_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static struct ccu_common *sun50i_a64_de2_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	&mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	&mixer1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	&wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	&bus_mixer0_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	&bus_mixer1_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	&bus_wb_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	&mixer0_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	&mixer1_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	&wb_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	&bus_rot_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	&rot_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	&rot_div_clk.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		[CLK_MIXER0]		= &mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		[CLK_MIXER1]		= &mixer1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		[CLK_WB]		= &wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		[CLK_ROT]		= &rot_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		[CLK_BUS_ROT]		= &bus_rot_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		[CLK_MIXER0_DIV]	= &mixer0_div_a83_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		[CLK_MIXER1_DIV]	= &mixer1_div_a83_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		[CLK_WB_DIV]		= &wb_div_a83_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		[CLK_ROT_DIV]		= &rot_div_a83_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.num	= CLK_NUMBER_WITH_ROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		[CLK_MIXER0]		= &mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		[CLK_MIXER1]		= &mixer1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		[CLK_WB]		= &wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.num	= CLK_NUMBER_WITHOUT_ROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		[CLK_MIXER0]		= &mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		[CLK_WB]		= &wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.num	= CLK_NUMBER_WITHOUT_ROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.hws	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		[CLK_MIXER0]		= &mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		[CLK_MIXER1]		= &mixer1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		[CLK_WB]		= &wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		[CLK_ROT]		= &rot_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		[CLK_BUS_MIXER0]	= &bus_mixer0_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		[CLK_BUS_MIXER1]	= &bus_mixer1_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		[CLK_BUS_WB]		= &bus_wb_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		[CLK_BUS_ROT]		= &bus_rot_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		[CLK_MIXER0_DIV]	= &mixer0_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		[CLK_MIXER1_DIV]	= &mixer1_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		[CLK_WB_DIV]		= &wb_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		[CLK_ROT_DIV]		= &rot_div_clk.common.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.num	= CLK_NUMBER_WITH_ROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	[RST_MIXER0]	= { 0x08, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * Mixer1 reset line is shared with wb, so only RST_WB is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * exported here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	[RST_WB]	= { 0x08, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	[RST_ROT]	= { 0x08, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct ccu_reset_map sun8i_h3_de2_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	[RST_MIXER0]	= { 0x08, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * Mixer1 reset line is shared with wb, so only RST_WB is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * exported here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * V3s doesn't have mixer1, so it also shares this struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	[RST_WB]	= { 0x08, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct ccu_reset_map sun50i_a64_de2_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	[RST_MIXER0]	= { 0x08, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	[RST_MIXER1]	= { 0x08, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	[RST_WB]	= { 0x08, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	[RST_ROT]	= { 0x08, BIT(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct ccu_reset_map sun50i_h5_de2_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	[RST_MIXER0]	= { 0x08, BIT(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	[RST_MIXER1]	= { 0x08, BIT(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	[RST_WB]	= { 0x08, BIT(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.ccu_clks	= sun8i_a83t_de2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.num_ccu_clks	= ARRAY_SIZE(sun8i_a83t_de2_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.hw_clks	= &sun8i_a83t_de2_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.resets		= sun8i_a83t_de2_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.ccu_clks	= sun8i_h3_de2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.hw_clks	= &sun8i_h3_de2_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.resets		= sun8i_h3_de2_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.num_resets	= ARRAY_SIZE(sun8i_h3_de2_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.ccu_clks	= sun50i_a64_de2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.hw_clks	= &sun50i_a64_de2_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.resets		= sun8i_a83t_de2_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.ccu_clks	= sun8i_v3s_de2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_de2_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.hw_clks	= &sun8i_v3s_de2_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.resets		= sun8i_a83t_de2_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.num_resets	= ARRAY_SIZE(sun8i_a83t_de2_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.ccu_clks	= sun50i_a64_de2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_de2_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.hw_clks	= &sun50i_a64_de2_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.resets		= sun50i_a64_de2_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.num_resets	= ARRAY_SIZE(sun50i_a64_de2_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.ccu_clks	= sun8i_h3_de2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_de2_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.hw_clks	= &sun8i_h3_de2_hw_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.resets		= sun50i_h5_de2_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int sunxi_de2_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct clk *bus_clk, *mod_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	const struct sunxi_ccu_desc *ccu_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	ccu_desc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (!ccu_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	reg = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	bus_clk = devm_clk_get(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (IS_ERR(bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		ret = PTR_ERR(bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	mod_clk = devm_clk_get(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (IS_ERR(mod_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		ret = PTR_ERR(mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		ret = PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				"Couldn't get reset control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	/* The clocks need to be enabled for us to access the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ret = clk_prepare_enable(bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	ret = clk_prepare_enable(mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		goto err_disable_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* The reset control needs to be asserted for the controls to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			"Couldn't deassert reset control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		goto err_disable_mod_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		goto err_assert_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err_assert_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err_disable_mod_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	clk_disable_unprepare(mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err_disable_bus_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	clk_disable_unprepare(bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct of_device_id sunxi_de2_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.compatible = "allwinner,sun8i-a83t-de2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.data = &sun8i_a83t_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.compatible = "allwinner,sun8i-h3-de2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.data = &sun8i_h3_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.compatible = "allwinner,sun8i-r40-de2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.data = &sun8i_r40_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.compatible = "allwinner,sun8i-v3s-de2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.data = &sun8i_v3s_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.compatible = "allwinner,sun50i-a64-de2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.data = &sun50i_a64_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		.compatible = "allwinner,sun50i-h5-de2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		.data = &sun50i_h5_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.compatible = "allwinner,sun50i-h6-de3-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.data = &sun50i_h5_de2_clk_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct platform_driver sunxi_de2_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.probe	= sunxi_de2_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.name	= "sunxi-de2-clks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		.of_match_table	= sunxi_de2_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) builtin_platform_driver(sunxi_de2_clk_driver);